KMAC/MASKED Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.205m	15.112ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	101.839us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	28.488us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.480s	1.522ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.990s	5.164ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.460s	153.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	28.488us	20	20	100.00
		kmac_csr_aliasing	9.990s	5.164ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.870s	68.764us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	18.487us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.212h	116.876ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.582m	159.571ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	50.584m	326.917ms	5	5	100.00
		kmac_test_vectors_sha3_256	45.413m	75.824ms	5	5	100.00
		kmac_test_vectors_sha3_384	36.287m	114.093ms	5	5	100.00
		kmac_test_vectors_sha3_512	29.993m	434.471ms	5	5	100.00
		kmac_test_vectors_shake_128	4.768m	16.054ms	5	5	100.00
		kmac_test_vectors_shake_256	42.159m	60.880ms	5	5	100.00
		kmac_test_vectors_kmac	5.270s	861.861us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.440s	81.476us	5	5	100.00
V2	sideload	kmac_sideload	12.383m	94.755ms	50	50	100.00
V2	app	kmac_app	7.217m	33.968ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.376m	85.988ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.952m	35.310ms	50	50	100.00
V2	error	kmac_error	10.640m	82.939ms	50	50	100.00
V2	key_error	kmac_key_error	27.660s	8.250ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.001m	654.399us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	31.950s	455.057us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.772m	7.088ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.830s	1.899ms	50	50	100.00
V2	stress_all	kmac_stress_all	57.936m	309.769ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.130s	29.671us	50	50	100.00
V2	alert_test	kmac_alert_test	1.390s	18.884us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.060s	727.996us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.060s	727.996us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	101.839us	5	5	100.00
		kmac_csr_rw	1.300s	28.488us	20	20	100.00
		kmac_csr_aliasing	9.990s	5.164ms	5	5	100.00
		kmac_same_csr_outstanding	2.680s	461.009us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	101.839us	5	5	100.00
		kmac_csr_rw	1.300s	28.488us	20	20	100.00
		kmac_csr_aliasing	9.990s	5.164ms	5	5	100.00
		kmac_same_csr_outstanding	2.680s	461.009us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	30.506us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	30.506us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	30.506us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	30.506us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.190s	334.583us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	2.353m	61.911ms	5	5	100.00
		kmac_tl_intg_err	4.210s	209.882us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.210s	209.882us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.830s	1.899ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.205m	15.112ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	12.383m	94.755ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	30.506us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.353m	61.911ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.353m	61.911ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.353m	61.911ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.205m	15.112ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.830s	1.899ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.353m	61.911ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	9.604m	27.400ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.205m	15.112ms	49	50	98.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.418m	12.095ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			882	890	99.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.89	92.58	99.89	78.17	95.53	98.89	97.88

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 2.kmac_stress_all_with_rand_reset.70893933705523956808704845856555204453300332734468815774487527309967514875056
      Line 172, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3367472446 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3367472446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.72650145197032884049192187979901312811266796424505865872456423051946630899148
      Line 273, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3546964787 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3546964787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

  • Test kmac_stress_all has 1 failures.

    • 16.kmac_stress_all.18396819277124058094307547423425288680130159462857047082243697392110569090349
      Line 766, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log

        UVM_ERROR @ 9234955098 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 9234955098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_smoke has 1 failures.

    • 17.kmac_smoke.80090079238730545543253854057345855992385251436367433035316233223446398594912
      Line 67, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/17.kmac_smoke/latest/run.log

        UVM_ERROR @  70764311 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  70764311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 4.kmac_shadow_reg_errors_with_csr_rw.29694458654617478237248450563567017750935831039820573342400444072024394981812
      Line 68, in log /workspaces/repo/scratch/os_regression_2024_09_03/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  39954070 ps: (kmac_csr_assert_fpv.sv:412) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  39954070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.02_11.30.21
• 2024.08.29_23.12.23
• 2024.08.28_06.55.56
• 2024.08.26_02.17.10
• 2024.08.24_20.04.20
• 2024.08.22_14.05.55
• 2024.08.20_07.49.55