KMAC/MASKED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.928m	31.584ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.270s	44.235us	5	5	100.00
V1	csr_rw	kmac_csr_rw	48.646s		19	20	95.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.200s	5.226ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.850s	942.871us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	48.594s		19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	48.646s		19	20	95.00
		kmac_csr_aliasing	8.850s	942.871us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.920s	20.040us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.640s	41.757us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	long_msg_and_output	kmac_long_msg_and_output	1.592h	136.427ms	49	50	98.00
V2	burst_write	kmac_burst_write	28.000m	126.301ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.284m	163.367ms	5	5	100.00
		kmac_test_vectors_sha3_256	46.328m	245.616ms	5	5	100.00
		kmac_test_vectors_sha3_384	37.113m	122.783ms	5	5	100.00
		kmac_test_vectors_sha3_512	35.690m	49.497ms	5	5	100.00
		kmac_test_vectors_shake_128	39.392m	21.390ms	5	5	100.00
		kmac_test_vectors_shake_256	44.399m	244.180ms	5	5	100.00
		kmac_test_vectors_kmac	4.220s	739.756us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.640s	235.555us	5	5	100.00
V2	sideload	kmac_sideload	12.815m	70.034ms	50	50	100.00
V2	app	kmac_app	9.957m	19.642ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.524m	9.475ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.261m	65.176ms	50	50	100.00
V2	error	kmac_error	10.271m	14.457ms	49	50	98.00
V2	key_error	kmac_key_error	30.300s	13.755ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	59.180s	5.823ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.520s	5.666ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.839m	7.569ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.710s	734.085us	50	50	100.00
V2	stress_all	kmac_stress_all	56.697m	96.883ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.100s	12.022us	50	50	100.00
V2	alert_test	kmac_alert_test	1.410s	32.870us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.990s	161.118us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.990s	161.118us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.270s	44.235us	5	5	100.00
		kmac_csr_rw	48.646s		19	20	95.00
		kmac_csr_aliasing	8.850s	942.871us	5	5	100.00
		kmac_same_csr_outstanding	3.040s	197.030us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.270s	44.235us	5	5	100.00
		kmac_csr_rw	48.646s		19	20	95.00
		kmac_csr_aliasing	8.850s	942.871us	5	5	100.00
		kmac_same_csr_outstanding	3.040s	197.030us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	48.564s		19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	48.564s		19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	48.564s		19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	48.564s		19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.230s	2.139ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.631m	8.650ms	5	5	100.00
		kmac_tl_intg_err	4.800s	304.988us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.800s	304.988us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.710s	734.085us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.928m	31.584ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	12.815m	70.034ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	48.564s		19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.631m	8.650ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.631m	8.650ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.631m	8.650ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.928m	31.584ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.710s	734.085us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.631m	8.650ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.816m	13.483ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.928m	31.584ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.805m	4.078ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			881	890	98.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.89	92.58	99.89	78.17	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.38982986774455893445370028377326121120302502952351532155148976777959767089786
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1568274226 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1568274226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.101486404641794647495170713338677958969862329571563153259996558482583040478683
    Line 242, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1939465725 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1939465725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Job returned non-zero exit code has 3 failures:

Test kmac_csr_rw has 1 failures.

18.kmac_csr_rw.81860198331494271866120228867898973759588199079882122827252414223511432880765
Log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_csr_mem_rw_with_rand_reset has 1 failures.

18.kmac_csr_mem_rw_with_rand_reset.49341946688995360754486016595395675841212664392291723837551155175620829488503
Log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_shadow_reg_errors has 1 failures.

19.kmac_shadow_reg_errors.75651376360386038177900713874564962131235358798454670723643371055408720830361
Log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  9 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 21.kmac_error.22571887239643225207504436906918321485741045357348300842061993753074017846183
    Line 828, in log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 46.kmac_long_msg_and_output.85646822840537768797895275293736207239054354494562590058953608185658844230698
    Log /workspaces/repo/scratch/os_regression_2024_09_08/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest/run.log
```
  Job timed out after 120 minutes
```