KMAC/MASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.795m	3.732ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.090s	35.577us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.090s	50.796us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.200s	5.344ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.060s	286.919us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.540s	410.433us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.090s	50.796us	20	20	100.00
		kmac_csr_aliasing	7.060s	286.919us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	13.547us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	147.172us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.527h	145.351ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.770m	14.860ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	47.186m	60.741ms	5	5	100.00
		kmac_test_vectors_sha3_256	46.293m	169.783ms	5	5	100.00
		kmac_test_vectors_sha3_384	35.691m	58.600ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.380m	939.412ms	5	5	100.00
		kmac_test_vectors_shake_128	59.564m	212.123ms	5	5	100.00
		kmac_test_vectors_shake_256	35.047m	69.258ms	5	5	100.00
		kmac_test_vectors_kmac	4.590s	150.817us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.030s	360.167us	5	5	100.00
V2	sideload	kmac_sideload	10.726m	14.165ms	50	50	100.00
V2	app	kmac_app	8.650m	76.688ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.592m	24.429ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.417m	35.711ms	50	50	100.00
V2	error	kmac_error	12.090m	43.987ms	49	50	98.00
V2	key_error	kmac_key_error	27.200s	7.304ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.980s	831.943us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.960s	5.810ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.571m	11.376ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	57.420s	13.221ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.395h	122.948ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.990s	19.994us	50	50	100.00
V2	alert_test	kmac_alert_test	1.490s	29.898us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.590s	61.723us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.590s	61.723us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.090s	35.577us	5	5	100.00
		kmac_csr_rw	1.090s	50.796us	20	20	100.00
		kmac_csr_aliasing	7.060s	286.919us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	247.835us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.090s	35.577us	5	5	100.00
		kmac_csr_rw	1.090s	50.796us	20	20	100.00
		kmac_csr_aliasing	7.060s	286.919us	5	5	100.00
		kmac_same_csr_outstanding	2.540s	247.835us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.250s	188.895us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.250s	188.895us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.250s	188.895us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.250s	188.895us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.710s	152.366us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.770m	5.479ms	5	5	100.00
		kmac_tl_intg_err	4.620s	219.328us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.620s	219.328us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	57.420s	13.221ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.795m	3.732ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.726m	14.165ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.250s	188.895us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.770m	5.479ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.770m	5.479ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.770m	5.479ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.795m	3.732ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	57.420s	13.221ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.770m	5.479ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.717m	6.156ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.795m	3.732ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.995m	21.886ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			884	890	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.23	97.91	92.65	99.89	76.76	95.59	99.05	97.73

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 3.kmac_stress_all_with_rand_reset.93161659127642261268114276965231076448100444453479946661754777213885362526630
    Line 198, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41584293852 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 41584293852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.4535481352719891084659021112026550834680368901510298262202072801823094185849
    Line 191, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6707278024 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6707278024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 1 failures.
  - 18.kmac_error.106390869122706881795616005199807069432130916183801444978415251910351029525160
    Line 606, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/18.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 21.kmac_burst_write.51788958628073731390021144976165720723256305097486308428543268703332442867655
    Line 949, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25b1acbf68`