KMAC/MASKED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.298m	8.544ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.540s	27.461us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.800s	133.174us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	25.480s	8.888ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.340s	546.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	25.310s		19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	133.174us	20	20	100.00
		kmac_csr_aliasing	9.340s	546.010us	5	5	100.00
V1	mem_walk	kmac_mem_walk	25.173s		4	5	80.00
V1	mem_partial_access	kmac_mem_partial_access	25.124s		4	5	80.00
V1		TOTAL			111	115	96.52
V2	long_msg_and_output	kmac_long_msg_and_output	1.442h	468.028ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.476m	27.415ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.030m	72.168ms	5	5	100.00
		kmac_test_vectors_sha3_256	49.071m	308.848ms	5	5	100.00
		kmac_test_vectors_sha3_384	38.578m	492.734ms	5	5	100.00
		kmac_test_vectors_sha3_512	29.721m	102.177ms	5	5	100.00
		kmac_test_vectors_shake_128	58.218m	288.157ms	5	5	100.00
		kmac_test_vectors_shake_256	44.770m	113.656ms	5	5	100.00
		kmac_test_vectors_kmac	4.330s	310.828us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.240s	117.877us	5	5	100.00
V2	sideload	kmac_sideload	11.482m	52.941ms	50	50	100.00
V2	app	kmac_app	9.577m	80.959ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.946m	72.160ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.227m	18.662ms	50	50	100.00
V2	error	kmac_error	10.079m	75.108ms	50	50	100.00
V2	key_error	kmac_key_error	24.170s	6.315ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.264m	2.156ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.161m	9.284ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.253m	65.263ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.260s	503.787us	50	50	100.00
V2	stress_all	kmac_stress_all	57.151m	78.454ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.350s	35.600us	50	50	100.00
V2	alert_test	kmac_alert_test	1.450s	16.349us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.520s	184.165us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.520s	184.165us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.540s	27.461us	5	5	100.00
		kmac_csr_rw	1.800s	133.174us	20	20	100.00
		kmac_csr_aliasing	9.340s	546.010us	5	5	100.00
		kmac_same_csr_outstanding	25.351s		19	20	95.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.540s	27.461us	5	5	100.00
		kmac_csr_rw	1.800s	133.174us	20	20	100.00
		kmac_csr_aliasing	9.340s	546.010us	5	5	100.00
		kmac_same_csr_outstanding	25.351s		19	20	95.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	25.256s		19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	25.256s		19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	25.256s		19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	25.256s		19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	25.214s		18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	2.313m	31.344ms	5	5	100.00
		kmac_tl_intg_err	6.040s	1.022ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.040s	1.022ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.260s	503.787us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.298m	8.544ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	11.482m	52.941ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	25.256s		19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.313m	31.344ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.313m	31.344ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.313m	31.344ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.298m	8.544ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.260s	503.787us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.313m	31.344ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.205m	11.380ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.298m	8.544ms	49	50	98.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.846m	8.020ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			877	890	98.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	4	50.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	97.88	92.58	99.89	78.17	95.51	98.91	97.88

Failure Buckets

Job returned non-zero exit code has 7 failures:

Test kmac_same_csr_outstanding has 1 failures.

1.kmac_same_csr_outstanding.60381461284684993461043761374091205301885651888877642019218553068480524872875
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_csr_mem_rw_with_rand_reset has 1 failures.

1.kmac_csr_mem_rw_with_rand_reset.113665765745316785854572621621242272426947387770994599547651142933719447649881
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_shadow_reg_errors has 1 failures.

2.kmac_shadow_reg_errors.41882603842647467295043220513360564130218135170978971016719052848908777109253
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

2.kmac_shadow_reg_errors_with_csr_rw.61595417406586799746551348252680000094217154693215398171432443052966292205301
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

3.kmac_shadow_reg_errors_with_csr_rw.60508162692574335550315111380338983876777618164093533876856933955173984175622
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_mem_walk has 1 failures.

2.kmac_mem_walk.115741606785642450396488564537628607036110432779129328373441032007882112543810
Log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/2.kmac_mem_walk/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 24 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more tests.

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 3.kmac_stress_all_with_rand_reset.84354749479820092449819489777194879071969027416134723496924645344526168734185
    Line 248, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3349807160 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3349807160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.103067494194397615961216500920915480755280208653242891747609308634600351217893
    Line 75, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109256214 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 109256214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.85421883524752188378802354674816136462144859872601919862003015660459701866561
    Line 190, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4045877610 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4045877610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_smoke has 1 failures.
  - 24.kmac_smoke.83482776569441516083008744038977781716478567996360087122301836096261075252938
    Line 67, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/24.kmac_smoke/latest/run.log
```
  UVM_ERROR @ 125488542 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 125488542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 31.kmac_key_error.107229487917894397695438359378867410767711553913549662853369903330867080133187
    Line 68, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_masked-sim-vcs/31.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 235071241 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 235071241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```