KMAC/MASKED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.893m	38.626ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	92.826us	5	5	100.00
V1	csr_rw	kmac_csr_rw	25.652s		19	20	95.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.610s	9.026ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.140s	981.921us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.510s	142.206us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	25.652s		19	20	95.00
		kmac_csr_aliasing	5.140s	981.921us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	13.314us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	169.743us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.651h	609.368ms	50	50	100.00
V2	burst_write	kmac_burst_write	32.161m	72.594ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.468m	163.011ms	5	5	100.00
		kmac_test_vectors_sha3_256	51.837m	429.555ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.636m	54.637ms	5	5	100.00
		kmac_test_vectors_sha3_512	25.949m	33.165ms	5	5	100.00
		kmac_test_vectors_shake_128	54.376m	261.762ms	5	5	100.00
		kmac_test_vectors_shake_256	53.837m	88.749ms	5	5	100.00
		kmac_test_vectors_kmac	4.900s	95.132us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.720s	119.821us	5	5	100.00
V2	sideload	kmac_sideload	10.271m	91.817ms	50	50	100.00
V2	app	kmac_app	7.341m	83.652ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.980m	26.792ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.281m	31.304ms	50	50	100.00
V2	error	kmac_error	12.435m	20.697ms	50	50	100.00
V2	key_error	kmac_key_error	31.020s	15.986ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.033m	1.459ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	54.470s	6.319ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.063m	75.071ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.730s	708.070us	50	50	100.00
V2	stress_all	kmac_stress_all	1.281h	174.332ms	50	50	100.00
V2	intr_test	kmac_intr_test	25.681s		49	50	98.00
V2	alert_test	kmac_alert_test	1.540s	63.057us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.970s	149.588us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.970s	149.588us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	92.826us	5	5	100.00
		kmac_csr_rw	25.652s		19	20	95.00
		kmac_csr_aliasing	5.140s	981.921us	5	5	100.00
		kmac_same_csr_outstanding	25.619s		19	20	95.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	92.826us	5	5	100.00
		kmac_csr_rw	25.652s		19	20	95.00
		kmac_csr_aliasing	5.140s	981.921us	5	5	100.00
		kmac_same_csr_outstanding	25.619s		19	20	95.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.890s	178.131us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.890s	178.131us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.890s	178.131us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.890s	178.131us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.960s	488.344us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.956m	13.546ms	5	5	100.00
		kmac_tl_intg_err	5.010s	1.079ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.010s	1.079ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.730s	708.070us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.893m	38.626ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.271m	91.817ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.890s	178.131us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.956m	13.546ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.956m	13.546ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.956m	13.546ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.893m	38.626ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.730s	708.070us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.956m	13.546ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.665m	48.654ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.893m	38.626ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.061m	23.552ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			881	890	98.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.90	92.65	99.89	76.06	95.57	99.07	97.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.31663787206547295313399457065004539039575751769909047331714958263435093096383
    Line 177, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1310136204 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1310136204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.43953010185387693635804206236457175136372032218228644843285646519981230770293
    Line 174, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6350163743 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6350163743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Job returned non-zero exit code has 3 failures:

Test kmac_intr_test has 1 failures.

14.kmac_intr_test.18292817835668743839944708769620135078369669244939678403654497452584401682250
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  2 23:18 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_csr_rw has 1 failures.

14.kmac_csr_rw.91265261754095752785511980194186317132059700552984286966953280008227322170331
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  2 23:18 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_same_csr_outstanding has 1 failures.

14.kmac_same_csr_outstanding.50402824609805555275703935131754872782910572649375749000364267753774898029810
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  2 23:18 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255