KMAC/MASKED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.007m	5.484ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.420s	39.241us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.840s	98.952us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.810s	998.594us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.350s	2.144ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.760s	269.641us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	98.952us	20	20	100.00
		kmac_csr_aliasing	9.350s	2.144ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.090s	22.185us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.810s	65.676us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.234h	114.579ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.545m	40.498ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.530m	114.866ms	5	5	100.00
		kmac_test_vectors_sha3_256	39.917m	242.381ms	5	5	100.00
		kmac_test_vectors_sha3_384	35.007m	945.536ms	4	5	80.00
		kmac_test_vectors_sha3_512	24.489m	170.271ms	5	5	100.00
		kmac_test_vectors_shake_128	38.715m	21.359ms	5	5	100.00
		kmac_test_vectors_shake_256	53.903m	360.851ms	5	5	100.00
		kmac_test_vectors_kmac	4.380s	515.910us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.310s	375.688us	5	5	100.00
V2	sideload	kmac_sideload	11.869m	65.999ms	50	50	100.00
V2	app	kmac_app	6.409m	13.546ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.684m	30.502ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.572m	19.250ms	50	50	100.00
V2	error	kmac_error	9.355m	47.521ms	50	50	100.00
V2	key_error	kmac_key_error	22.890s	3.515ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.770s	7.782ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.910s	421.972us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.346m	8.148ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	51.310s	971.616us	50	50	100.00
V2	stress_all	kmac_stress_all	52.232m	115.687ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.250s	18.006us	50	50	100.00
V2	alert_test	kmac_alert_test	1.450s	246.130us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.390s	267.605us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.390s	267.605us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.420s	39.241us	5	5	100.00
		kmac_csr_rw	1.840s	98.952us	20	20	100.00
		kmac_csr_aliasing	9.350s	2.144ms	5	5	100.00
		kmac_same_csr_outstanding	3.410s	1.503ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.420s	39.241us	5	5	100.00
		kmac_csr_rw	1.840s	98.952us	20	20	100.00
		kmac_csr_aliasing	9.350s	2.144ms	5	5	100.00
		kmac_same_csr_outstanding	3.410s	1.503ms	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	39.691us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	39.691us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	39.691us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	39.691us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.350s	445.148us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.496m	56.375ms	5	5	100.00
		kmac_tl_intg_err	5.480s	1.152ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.480s	1.152ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	51.310s	971.616us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.007m	5.484ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	11.869m	65.999ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	39.691us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.496m	56.375ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.496m	56.375ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.496m	56.375ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.007m	5.484ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	51.310s	971.616us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.496m	56.375ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.004m	13.132ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.007m	5.484ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.652m	3.113ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			882	890	99.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.90	92.65	99.89	76.76	95.57	99.07	97.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.102387719160705071788053732760187130055283577805597790007454177580369520264317
    Line 226, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22509087995 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 22509087995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.112079705045944335038662143965927059370653784748258284600317869649246351689487
    Line 339, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9852789171 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9852789171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 1.kmac_test_vectors_sha3_384.75958861938537019196860641184806370885962240986122004845029070750905210358684
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  93265465 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  93265465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/MASKED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `7e34e67ade`