KMAC/MASKED Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.148m	21.977ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.750s	19.836us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.870s	52.213us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.560s	1.440ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	14.070s	8.655ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.860s	144.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.870s	52.213us	20	20	100.00
		kmac_csr_aliasing	14.070s	8.655ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.250s	30.195us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.360s	155.869us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.483h	238.268ms	49	50	98.00
V2	burst_write	kmac_burst_write	29.025m	143.128ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.086m	84.783ms	5	5	100.00
		kmac_test_vectors_sha3_256	47.855m	120.027ms	5	5	100.00
		kmac_test_vectors_sha3_384	35.386m	91.029ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.930m	123.378ms	5	5	100.00
		kmac_test_vectors_shake_128	43.794m	21.266ms	5	5	100.00
		kmac_test_vectors_shake_256	48.268m	505.561ms	5	5	100.00
		kmac_test_vectors_kmac	4.860s	281.840us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.920s	630.246us	5	5	100.00
V2	sideload	kmac_sideload	10.512m	15.975ms	50	50	100.00
V2	app	kmac_app	8.716m	52.392ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	10.787m	97.157ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.842m	32.072ms	50	50	100.00
V2	error	kmac_error	10.125m	6.365ms	50	50	100.00
V2	key_error	kmac_key_error	32.360s	18.885ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	13.690s	1.617ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.710s	4.054ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	53.280s	6.995ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.030m	15.478ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	56.660s	1.891ms	50	50	100.00
V2	stress_all	kmac_stress_all	58.347m	93.584ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.320s	63.072us	50	50	100.00
V2	alert_test	kmac_alert_test	1.430s	169.703us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.860s	715.499us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.860s	715.499us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.750s	19.836us	5	5	100.00
		kmac_csr_rw	1.870s	52.213us	20	20	100.00
		kmac_csr_aliasing	14.070s	8.655ms	5	5	100.00
		kmac_same_csr_outstanding	3.640s	545.179us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.750s	19.836us	5	5	100.00
		kmac_csr_rw	1.870s	52.213us	20	20	100.00
		kmac_csr_aliasing	14.070s	8.655ms	5	5	100.00
		kmac_same_csr_outstanding	3.640s	545.179us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.300s	58.405us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.300s	58.405us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.300s	58.405us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.300s	58.405us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.220s	119.359us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.254m	29.352ms	5	5	100.00
		kmac_tl_intg_err	6.830s	3.656ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.830s	3.656ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	56.660s	1.891ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.148m	21.977ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	10.512m	15.975ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.300s	58.405us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.254m	29.352ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.254m	29.352ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.254m	29.352ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.148m	21.977ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	56.660s	1.891ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.254m	29.352ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.782m	74.640ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.148m	21.977ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.129m	20.649ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			934	940	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	26	26	25	96.15
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.73	98.11	92.78	99.89	79.58	95.93	99.07	97.73

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
  • Test kmac_stress_all_with_rand_reset has 4 failures.

    • 1.kmac_stress_all_with_rand_reset.3496783011250985906578620635437414934659102933240701691825319765177257362911
      Line 194, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2841614836 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2841614836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.kmac_stress_all_with_rand_reset.94266399068666585434325654722609604611424637701378535102156673005492028625940
      Line 148, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4405570661 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 4405570661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

  • Test kmac_long_msg_and_output has 1 failures.

    • 7.kmac_long_msg_and_output.72440093166270108113211633703848262042525273793357240999862244581297248509728
      Line 67, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest/run.log

        UVM_ERROR @  50992995 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  50992995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_smoke has 1 failures.

    • 30.kmac_smoke.53069165357939968329574263870041417477640952259563445856673074769798036875516
      Line 67, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_smoke/latest/run.log

        UVM_ERROR @  63824480 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  63824480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.10_10.14.52
• 2024.10.04_00.41.45
• 2024.09.25_11.00.45
• 2024.09.19_09.04.31
• 2024.09.12_10.16.09
• 2024.09.10_08.11.01
• 2024.09.05_04.20.34