KMAC/MASKED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	3.380m	21.923ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	55.424us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.830s	113.180us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	24.430s	1.479ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.150s	1.591ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.940s	282.770us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.830s	113.180us	20	20	100.00
		kmac_csr_aliasing	11.150s	1.591ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.190s	39.508us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.240s	411.234us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.374h	89.213ms	50	50	100.00
V2	burst_write	kmac_burst_write	30.368m	195.700ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	49.931m	329.405ms	5	5	100.00
		kmac_test_vectors_sha3_256	38.764m	19.016ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.639m	103.930ms	5	5	100.00
		kmac_test_vectors_sha3_512	27.254m	197.508ms	5	5	100.00
		kmac_test_vectors_shake_128	55.408m	361.188ms	5	5	100.00
		kmac_test_vectors_shake_256	43.671m	230.092ms	5	5	100.00
		kmac_test_vectors_kmac	5.470s	440.490us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.860s	58.971us	5	5	100.00
V2	sideload	kmac_sideload	10.456m	31.058ms	50	50	100.00
V2	app	kmac_app	9.341m	91.682ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.455m	46.295ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.439m	30.335ms	50	50	100.00
V2	error	kmac_error	9.598m	47.540ms	50	50	100.00
V2	key_error	kmac_key_error	22.910s	3.090ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.120s	1.610ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.300s	1.990ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.022m	8.170ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.340s	620.724us	50	50	100.00
V2	stress_all	kmac_stress_all	47.897m	603.103ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.340s	17.875us	50	50	100.00
V2	alert_test	kmac_alert_test	1.510s	31.740us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	7.120s	886.664us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	7.120s	886.664us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	55.424us	5	5	100.00
		kmac_csr_rw	1.830s	113.180us	20	20	100.00
		kmac_csr_aliasing	11.150s	1.591ms	5	5	100.00
		kmac_same_csr_outstanding	4.280s	526.875us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	55.424us	5	5	100.00
		kmac_csr_rw	1.830s	113.180us	20	20	100.00
		kmac_csr_aliasing	11.150s	1.591ms	5	5	100.00
		kmac_same_csr_outstanding	4.280s	526.875us	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.300s	56.004us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.300s	56.004us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.300s	56.004us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.300s	56.004us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.480s	249.548us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.052m	8.960ms	5	5	100.00
		kmac_tl_intg_err	7.960s	378.097us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.960s	378.097us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.340s	620.724us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	3.380m	21.923ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.456m	31.058ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.300s	56.004us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.052m	8.960ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.052m	8.960ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.052m	8.960ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	3.380m	21.923ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.340s	620.724us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.052m	8.960ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.687m	74.105ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	3.380m	21.923ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.200m	10.455ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			887	890	99.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	25	100.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.43	97.90	92.68	99.89	78.17	95.57	99.07	97.73

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 0.kmac_stress_all_with_rand_reset.10825845920757331366641937752837425963241120814524804719719509249593398878789
      Line 94, in log /workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2560257596 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2560257596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.kmac_stress_all_with_rand_reset.105537209374154115393268625281430704146624874666214699272459824716358571162089
      Line 165, in log /workspaces/repo/scratch/os_regression_2024_10_08/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3187364124 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3187364124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

Past Results

• Latest
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• 2024.09.25_11.00.45
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