KMAC/UNMASKED Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.018m	5.450ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.150s	46.296us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	135.399us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.210s	5.540ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.930s	606.209us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.190s	83.705us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	135.399us	20	20	100.00
		kmac_csr_aliasing	10.930s	606.209us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	26.618us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.360s	235.071us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.818m	941.264ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.858m	36.308ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.790m	757.266ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.878m	1.009s	50	50	100.00
		kmac_test_vectors_sha3_384	25.626m	373.409ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.933m	538.315ms	50	50	100.00
		kmac_test_vectors_shake_128	1.554h	1.076s	50	50	100.00
		kmac_test_vectors_shake_256	1.341h	840.950ms	50	50	100.00
		kmac_test_vectors_kmac	5.530s	259.555us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.560s	996.896us	50	50	100.00
V2	sideload	kmac_sideload	7.003m	40.453ms	49	50	98.00
V2	app	kmac_app	5.207m	40.944ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.253m	48.981ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.142m	32.356ms	47	50	94.00
V2	error	kmac_error	6.663m	40.218ms	50	50	100.00
V2	key_error	kmac_key_error	6.800s	2.353ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.650s	20.162ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.950s	22.575ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.038m	14.469ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.010s	904.423us	50	50	100.00
V2	stress_all	kmac_stress_all	34.720m	144.888ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	83.889us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	20.973us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.850s	645.797us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.850s	645.797us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.150s	46.296us	5	5	100.00
		kmac_csr_rw	1.230s	135.399us	20	20	100.00
		kmac_csr_aliasing	10.930s	606.209us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	117.180us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.150s	46.296us	5	5	100.00
		kmac_csr_rw	1.230s	135.399us	20	20	100.00
		kmac_csr_aliasing	10.930s	606.209us	5	5	100.00
		kmac_same_csr_outstanding	2.760s	117.180us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.020s	201.395us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.020s	201.395us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.020s	201.395us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.020s	201.395us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.650s	1.246ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.311m	6.057ms	5	5	100.00
		kmac_tl_intg_err	5.620s	537.848us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.620s	537.848us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.010s	904.423us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.018m	5.450ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.003m	40.453ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.020s	201.395us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.311m	6.057ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.311m	6.057ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.311m	6.057ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.018m	5.450ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.010s	904.423us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.311m	6.057ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.644m	18.052ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.018m	5.450ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	54.816m	109.498ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1271	1290	98.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	96.65	92.55	100.00	92.05	94.67	98.82	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code

has 9 failures:

Test kmac_stress_all_with_rand_reset has 9 failures.

6.kmac_stress_all_with_rand_reset.4164638216
Line 1107, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 67990771552 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 67990771552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_stress_all_with_rand_reset.1151714656
Line 2026, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 82607071721 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 82607071721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 7 failures:

Test kmac_mubi has 1 failures.

3.kmac_mubi.2654243371
Line 331, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 31231582459 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (126 [0x7e] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31231582459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.469720057
Line 224, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 1262076142 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (82 [0x52] vs 163 [0xa3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1262076142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

30.kmac_stress_all.2165218128
Line 270, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3399404281 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (81 [0x51] vs 41 [0x29]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3399404281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

35.kmac_stress_all_with_rand_reset.4068344705
Line 483, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 22830733510 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (177 [0xb1] vs 68 [0x44]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 22830733510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

38.kmac_entropy_refresh.3895708778
Line 343, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 5091550767 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (76 [0x4c] vs 206 [0xce]) Mismatch between unmasked_digest[1] and dpi_digest[1]
  UVM_INFO @ 5091550767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.kmac_entropy_refresh.4142588793
Line 224, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 661393678 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (174 [0xae] vs 79 [0x4f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 661393678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.3716037219
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_burst_write has 1 failures.

8.kmac_burst_write.1409230793
Line 348, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_sideload has 1 failures.

21.kmac_sideload.2827587099
Line 311, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_sideload/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---