042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.039m | 4.148ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.130s | 67.857us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.130s | 27.031us | 15 | 20 | 75.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 22.680s | 3.285ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.310s | 1.677ms | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.170s | 49.920us | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.130s | 27.031us | 15 | 20 | 75.00 |
| kmac_csr_aliasing | 10.310s | 1.677ms | 3 | 5 | 60.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.710s | 12.784us | 3 | 5 | 60.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.470s | 38.138us | 4 | 5 | 80.00 |
| V1 | TOTAL | 102 | 115 | 88.70 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 45.516m | 130.988ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 14.055m | 41.851ms | 49 | 50 | 98.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 35.510m | 413.000ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 33.390m | 384.439ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 24.508m | 72.852ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 17.737m | 465.219ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.463h | 527.431ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.210h | 745.313ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 5.250s | 331.572us | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 5.300s | 1.924ms | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 6.834m | 21.241ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.504m | 179.492ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.917m | 29.971ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 5.838m | 21.663ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 6.452m | 142.515ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 5.820s | 8.590ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 38.630s | 41.250ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 38.630s | 5.733ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.016m | 7.393ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 22.340s | 5.878ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 41.565m | 122.217ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.810s | 27.653us | 43 | 50 | 86.00 |
| V2 | alert_test | kmac_alert_test | 0.870s | 19.517us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.730s | 148.920us | 15 | 20 | 75.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.730s | 148.920us | 15 | 20 | 75.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.130s | 67.857us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.130s | 27.031us | 15 | 20 | 75.00 | ||
| kmac_csr_aliasing | 10.310s | 1.677ms | 3 | 5 | 60.00 | ||
| kmac_same_csr_outstanding | 2.670s | 121.747us | 14 | 20 | 70.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.130s | 67.857us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.130s | 27.031us | 15 | 20 | 75.00 | ||
| kmac_csr_aliasing | 10.310s | 1.677ms | 3 | 5 | 60.00 | ||
| kmac_same_csr_outstanding | 2.670s | 121.747us | 14 | 20 | 70.00 | ||
| V2 | TOTAL | 1027 | 1050 | 97.81 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.360s | 76.780us | 12 | 20 | 60.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.360s | 76.780us | 12 | 20 | 60.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.360s | 76.780us | 12 | 20 | 60.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.360s | 76.780us | 12 | 20 | 60.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.690s | 1.303ms | 17 | 20 | 85.00 |
| V2S | tl_intg_err | kmac_sec_cm | 48.100s | 9.263ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.400s | 998.046us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.400s | 998.046us | 18 | 20 | 90.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 22.340s | 5.878ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.039m | 4.148ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 6.834m | 21.241ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.360s | 76.780us | 12 | 20 | 60.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 48.100s | 9.263ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 48.100s | 9.263ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 48.100s | 9.263ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.039m | 4.148ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 22.340s | 5.878ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 48.100s | 9.263ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 3.974m | 9.849ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.039m | 4.148ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 62 | 75 | 82.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 51.709m | 162.205ms | 40 | 50 | 80.00 |
| V3 | TOTAL | 40 | 50 | 80.00 | |||
| TOTAL | 1231 | 1290 | 95.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 3 | 37.50 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 2 | 40.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.46 | 96.58 | 92.46 | 100.00 | 88.64 | 94.67 | 98.84 | 97.02 |
Exit reason: Error: User command failed Job returned non-zero exit code has 44 failures:
Test kmac_shadow_reg_errors has 8 failures.
0.kmac_shadow_reg_errors.65501093921305907886794911602423416966848045791771755158134117330032672155474
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
[make]: simulate
cd /workspace/0.kmac_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459660626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1459660626 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.kmac_shadow_reg_errors.60629104776124872740113137756737437246395849068568959289863252160271952700689
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log
[make]: simulate
cd /workspace/1.kmac_shadow_reg_errors/latest && /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891324177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.3891324177 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test kmac_tl_errors has 5 failures.
0.kmac_tl_errors.22273000024345573097643868143909885061355852757320274238848243048269833112473
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/0.kmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548211609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.548211609 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.kmac_tl_errors.3483632859016153015282813052254422118006440750844857557624191653388352102250
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/3.kmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207915882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2207915882 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test kmac_tl_intg_err has 2 failures.
0.kmac_tl_intg_err.98082189535407615994866365725016225691270607112721516275879862895191083250044
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/0.kmac_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435117436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.2435117436 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.kmac_tl_intg_err.54197121804873833942245724257854783554116094921648402928717792480834103793775
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/4.kmac_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643005039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.3643005039 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_csr_aliasing has 2 failures.
0.kmac_csr_aliasing.85853364569033845019712729386505064656012847352650087100404300787898583694554
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/0.kmac_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011932890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.4011932890 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.kmac_csr_aliasing.55088309850827638233351698733944453264454714690770510091443999508648187457465
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/2.kmac_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222335417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3222335417 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_same_csr_outstanding has 6 failures.
0.kmac_same_csr_outstanding.5406347470092650513101634748139458795992599863421873168060331895761535239237
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/0.kmac_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848902725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1848902725 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:55 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.kmac_same_csr_outstanding.113982157729057321832363930000219405357625074331610919221323163546610476482585
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/1.kmac_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146926617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.2146926617 +enable_masking=0 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:56 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
... and 6 more tests.
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:
11.kmac_stress_all_with_rand_reset.47949927211436715017733402562227045922758972361957976846134984808359043158449
Line 372, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16225988313 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
UVM_INFO @ 16225988313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.kmac_stress_all_with_rand_reset.39826252288152651853144483277104649317524712094906870663564300527002508779466
Line 475, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8755625592 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
UVM_INFO @ 8755625592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:
Test kmac_app has 1 failures.
17.kmac_app.63799955442888497002649252948295550435291093026356632120590633474130195118724
Line 409, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_app/latest/run.log
UVM_FATAL @ 57069550083 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (141 [0x8d] vs 209 [0xd1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 57069550083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
45.kmac_stress_all.24029329110502161689809718720389483096180211749499262158943972842937869744496
Line 268, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_stress_all/latest/run.log
UVM_FATAL @ 2836424885 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (89 [0x59] vs 11 [0xb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2836424885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
47.kmac_entropy_refresh.3551156495014500270243921509564409531723546061255400085398269426416752453153
Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 4322768259 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (43 [0x2b] vs 8 [0x8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 4322768259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
29.kmac_key_error.114158607845063568329174846817111408032836484975621950201861137701130711599003
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_key_error/latest/run.log
UVM_ERROR @ 48595252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 48595252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
39.kmac_burst_write.11556406999072586013259222792273087832132801940568278432937436390972351067781
Line 376, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---