KMAC/UNMASKED Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.165m	18.083ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	36.694us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	32.582us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.720s	6.726ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.880s	461.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.400s	27.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	32.582us	20	20	100.00
		kmac_csr_aliasing	10.880s	461.089us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	47.689us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	92.453us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.684m	746.106ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.509m	148.648ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.326m	322.107ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.897m	354.852ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.767m	628.934ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.588m	443.329ms	50	50	100.00
		kmac_test_vectors_shake_128	1.689h	2.606s	50	50	100.00
		kmac_test_vectors_shake_256	1.474h	3.137s	50	50	100.00
		kmac_test_vectors_kmac	5.480s	869.016us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.970s	3.398ms	50	50	100.00
V2	sideload	kmac_sideload	7.365m	22.967ms	50	50	100.00
V2	app	kmac_app	5.781m	76.336ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.759m	29.373ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.764m	87.436ms	49	50	98.00
V2	error	kmac_error	7.836m	100.516ms	50	50	100.00
V2	key_error	kmac_key_error	8.740s	12.403ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.170s	26.446ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.990s	11.775ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.486m	34.440ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.050s	3.944ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.515m	445.676ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.800s	73.053us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	56.433us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.540s	251.669us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.540s	251.669us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	36.694us	5	5	100.00
		kmac_csr_rw	1.190s	32.582us	20	20	100.00
		kmac_csr_aliasing	10.880s	461.089us	5	5	100.00
		kmac_same_csr_outstanding	2.840s	732.282us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	36.694us	5	5	100.00
		kmac_csr_rw	1.190s	32.582us	20	20	100.00
		kmac_csr_aliasing	10.880s	461.089us	5	5	100.00
		kmac_same_csr_outstanding	2.840s	732.282us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	142.824us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	142.824us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	142.824us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	142.824us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.430s	517.041us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.246m	11.760ms	5	5	100.00
		kmac_tl_intg_err	5.080s	242.778us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.080s	242.778us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.050s	3.944ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.165m	18.083ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.365m	22.967ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	142.824us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.246m	11.760ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.246m	11.760ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.246m	11.760ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.165m	18.083ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.050s	3.944ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.246m	11.760ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.469m	60.817ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.165m	18.083ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.091m	100.721ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1275	1290	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.62	96.58	92.46	100.00	89.77	94.67	98.84	97.02

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:

  • Test kmac_stress_all_with_rand_reset has 12 failures.

    • 0.kmac_stress_all_with_rand_reset.91447353358753937761228811740436234216928790936102064458158343537134885979240
      Line 270, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  53283694 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @  53283694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.26116475651145125906768930642850451865774466710638217317984067634123912413770
      Line 944, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 297186423126 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 297186423126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 30.kmac_entropy_refresh.89475443262168530074837496851552156412487549433042260895842599447989772432279
      Line 371, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 12667420641 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (62 [0x3e] vs 10 [0xa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 12667420641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all has 1 failures.

    • 44.kmac_stress_all.3414985817084198145471976135466677636216070201561193587979620596058052085318
      Line 294, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_stress_all/latest/run.log

        UVM_FATAL @ 2372785736 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (95 [0x5f] vs 9 [0x9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 2372785736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 35.kmac_stress_all_with_rand_reset.10700030389339887557523736014481831668753196965033523133145921329687074629784
      Line 486, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 37232842589 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_xof_vseq] Check failed exp_digest[i] == act_digest[i] (213 [0xd5] vs 179 [0xb3]) Mismatch between exp_digest[0] and act_digest[0]
        UVM_INFO @ 37232842589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.01.11_03.09.52
• 2024.01.08_02.56.46
• 2024.01.04_01.21.04
• 2024.01.01_00.48.33
• 2023.12.28_03.22.05
• 2023.12.25_01.24.43
• 2023.12.21_00.14.32