KMAC/UNMASKED Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.178m	16.672ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	86.858us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	342.446us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.720s	1.592ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.300s	4.624ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	107.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	342.446us	20	20	100.00
		kmac_csr_aliasing	11.300s	4.624ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	15.841us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	44.995us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.228m	334.630ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.414m	154.479ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.481m	1.237s	50	50	100.00
		kmac_test_vectors_sha3_256	32.735m	94.506ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.534m	1.178s	50	50	100.00
		kmac_test_vectors_sha3_512	19.548m	954.605ms	50	50	100.00
		kmac_test_vectors_shake_128	1.834h	5.000s	49	50	98.00
		kmac_test_vectors_shake_256	1.316h	873.100ms	50	50	100.00
		kmac_test_vectors_kmac	5.260s	752.570us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.220s	251.746us	50	50	100.00
V2	sideload	kmac_sideload	7.982m	200.000ms	48	50	96.00
V2	app	kmac_app	4.936m	12.029ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.290m	22.692ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.634m	60.700ms	50	50	100.00
V2	error	kmac_error	7.317m	95.787ms	50	50	100.00
V2	key_error	kmac_key_error	6.700s	5.153ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.570s	3.485ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.030s	11.131ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.946m	171.286ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.070s	1.504ms	50	50	100.00
V2	stress_all	kmac_stress_all	29.399m	91.301ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	86.831us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	55.545us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.950s	240.287us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.950s	240.287us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	86.858us	5	5	100.00
		kmac_csr_rw	1.220s	342.446us	20	20	100.00
		kmac_csr_aliasing	11.300s	4.624ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	601.650us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	86.858us	5	5	100.00
		kmac_csr_rw	1.220s	342.446us	20	20	100.00
		kmac_csr_aliasing	11.300s	4.624ms	5	5	100.00
		kmac_same_csr_outstanding	2.690s	601.650us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.690s	259.255us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.690s	259.255us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.690s	259.255us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.690s	259.255us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.270s	157.774us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.079m	9.080ms	5	5	100.00
		kmac_tl_intg_err	5.040s	298.943us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.040s	298.943us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.070s	1.504ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.178m	16.672ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.982m	200.000ms	48	50	96.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.690s	259.255us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.079m	9.080ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.079m	9.080ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.079m	9.080ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.178m	16.672ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.070s	1.504ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.079m	9.080ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.401m	141.423ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.178m	16.672ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.124h	412.766ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1272	1290	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.80	96.58	92.46	100.00	90.91	94.67	98.84	97.16

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 1.kmac_stress_all_with_rand_reset.50841636314448935538204245296474894733847932711902255565897100939398436712795
    Line 982, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21260075242 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21260075242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.kmac_stress_all_with_rand_reset.64963616995410096426051052883882068534737110289899979464158436031223487330993
    Line 886, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52481214496 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 52481214496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
- Test kmac_sideload has 2 failures.
  - 1.kmac_sideload.27655374889295474768064475375402159347534353021002522994305655901398142258617
    Line 436, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_sideload.8898757928176714267808687399453448856455666813491069956726979204137602709451
    Line 435, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 2 failures.
  - 8.kmac_burst_write.18828338988610210287523612989848411777732314666050028572908463775263196968419
    Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_burst_write.44941817843073172147123179640914103409974129356424372202950749838163180712685
    Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 20.kmac_test_vectors_shake_128.29018085774543212542111645327956016539018038304160437286341258841414793966208
    Line 2035, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 3 failures.

2.kmac_app.97433312690338728663662125820269450112715608185373698276162675997258572815402
Line 389, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_app/latest/run.log

  UVM_FATAL @ 36579182843 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 36579182843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_app.101689946361522564663604640793765322278644510250776678973308570211675823779883
Line 310, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_app/latest/run.log

  UVM_FATAL @ 5475291547 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (30 [0x1e] vs 202 [0xca]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5475291547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_mubi has 1 failures.

7.kmac_mubi.1637000804654060290627565144696432252307559331888539540713229592681739224908
Line 300, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 4854377674 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (190 [0xbe] vs 169 [0xa9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4854377674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---