KMAC/UNMASKED Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.158m	16.436ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	53.730us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	36.219us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.770s	1.211ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.800s	468.025us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.410s	99.805us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	36.219us	20	20	100.00
		kmac_csr_aliasing	10.800s	468.025us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	13.989us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	35.812us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.634m	2.691s	50	50	100.00
V2	burst_write	kmac_burst_write	14.319m	165.673ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.085m	1.064s	50	50	100.00
		kmac_test_vectors_sha3_256	32.597m	98.130ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.415m	72.912ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.984m	176.700ms	50	50	100.00
		kmac_test_vectors_shake_128	1.578h	1.625s	50	50	100.00
		kmac_test_vectors_shake_256	1.349h	2.705s	50	50	100.00
		kmac_test_vectors_kmac	5.320s	1.024ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.310s	4.776ms	50	50	100.00
V2	sideload	kmac_sideload	6.737m	28.985ms	50	50	100.00
V2	app	kmac_app	5.080m	72.113ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.628m	27.235ms	8	10	80.00
V2	entropy_refresh	kmac_entropy_refresh	5.262m	14.078ms	49	50	98.00
V2	error	kmac_error	7.588m	42.730ms	50	50	100.00
V2	key_error	kmac_key_error	8.370s	8.169ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.600s	447.972us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.740s	6.766ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.567m	72.430ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.280s	1.040ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.311m	382.709ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.880s	23.739us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	31.180us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.530s	235.303us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.530s	235.303us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	53.730us	5	5	100.00
		kmac_csr_rw	1.240s	36.219us	20	20	100.00
		kmac_csr_aliasing	10.800s	468.025us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	741.880us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	53.730us	5	5	100.00
		kmac_csr_rw	1.240s	36.219us	20	20	100.00
		kmac_csr_aliasing	10.800s	468.025us	5	5	100.00
		kmac_same_csr_outstanding	2.810s	741.880us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	199.317us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	199.317us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	199.317us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	199.317us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.200s	407.431us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.071m	103.098ms	5	5	100.00
		kmac_tl_intg_err	5.420s	2.012ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.420s	2.012ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.280s	1.040ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.158m	16.436ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.737m	28.985ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	199.317us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.071m	103.098ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.071m	103.098ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.071m	103.098ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.158m	16.436ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.280s	1.040ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.071m	103.098ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.704m	69.546ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.158m	16.436ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.511m	95.058ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	96.58	92.49	100.00	89.77	94.67	98.84	96.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 4.kmac_stress_all_with_rand_reset.15068192217350897878799787213666104996325637551251218826806413233574553061005
    Line 601, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85461868680 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 85461868680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.107517601083314780386420188673834370103478622839069029678497928582706135973038
    Line 723, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116310190480 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 116310190480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app_with_partial_data has 2 failures.

1.kmac_app_with_partial_data.110517901929767925703813629072923282206156130505517094240813279634840472361381
Line 325, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 7281655600 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 4 [0x4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7281655600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_app_with_partial_data.101934674191615337967777037907203365984218473679021554780881308121631376740769
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 21707496177 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (65 [0x41] vs 5 [0x5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21707496177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

2.kmac_mubi.113377376722590358213177399814654751148839447053357508269557573946030297546166
Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 4417978785 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (87 [0x57] vs 47 [0x2f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4417978785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

27.kmac_app.50922443500845332511528228070393084254556017764506595861960252014354408323080
Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_app/latest/run.log

  UVM_FATAL @ 25179020941 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (158 [0x9e] vs 70 [0x46]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 25179020941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

41.kmac_entropy_refresh.21809439918998338049444980973591849738018866167383342498903041681875936052772
Line 309, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4746955914 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (120 [0x78] vs 223 [0xdf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4746955914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 29.kmac_burst_write.70206364206511859578504269970073414240964283979081448504673257302201948687095
    Line 302, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.kmac_burst_write.56894149696182337960983826377051382736722261339740381009219138812417146576059
    Line 392, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```