17d5a97c3b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.111m | 14.583ms | 49 | 50 | 98.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 118.454us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.210s | 62.116us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 20.080s | 4.304ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 11.660s | 2.218ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.450s | 55.566us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.210s | 62.116us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 11.660s | 2.218ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.740s | 15.231us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.580s | 139.641us | 5 | 5 | 100.00 |
V1 | TOTAL | 114 | 115 | 99.13 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 50.713m | 158.051ms | 50 | 50 | 100.00 |
V2 | burst_write | kmac_burst_write | 15.837m | 159.761ms | 47 | 50 | 94.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 35.749m | 101.668ms | 49 | 50 | 98.00 |
kmac_test_vectors_sha3_256 | 34.256m | 255.652ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 24.855m | 94.365ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 17.631m | 50.491ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.502h | 1.077s | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_256 | 1.279h | 913.128ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 5.550s | 988.130us | 49 | 50 | 98.00 | ||
kmac_test_vectors_kmac_xof | 5.670s | 2.067ms | 48 | 50 | 96.00 | ||
V2 | sideload | kmac_sideload | 6.521m | 39.523ms | 49 | 50 | 98.00 |
V2 | app | kmac_app | 5.458m | 52.500ms | 50 | 50 | 100.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 5.609m | 116.510ms | 9 | 10 | 90.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 5.174m | 14.390ms | 49 | 50 | 98.00 |
V2 | error | kmac_error | 8.188m | 117.733ms | 49 | 50 | 98.00 |
V2 | key_error | kmac_key_error | 7.090s | 12.567ms | 49 | 50 | 98.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 38.610s | 4.048ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 37.500s | 3.910ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.046m | 13.992ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 50.560s | 3.801ms | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 37.602m | 323.143ms | 48 | 50 | 96.00 |
V2 | intr_test | kmac_intr_test | 0.850s | 18.333us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.900s | 201.320us | 49 | 50 | 98.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.840s | 1.141ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.840s | 1.141ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 118.454us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.210s | 62.116us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.660s | 2.218ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.160s | 1.701ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 118.454us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.210s | 62.116us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 11.660s | 2.218ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.160s | 1.701ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1035 | 1050 | 98.57 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.420s | 62.389us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.420s | 62.389us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.420s | 62.389us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.420s | 62.389us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.120s | 1.203ms | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 1.169m | 5.307ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.800s | 324.519us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.800s | 324.519us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 50.560s | 3.801ms | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.111m | 14.583ms | 49 | 50 | 98.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 6.521m | 39.523ms | 49 | 50 | 98.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.420s | 62.389us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.169m | 5.307ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.169m | 5.307ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.169m | 5.307ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.111m | 14.583ms | 49 | 50 | 98.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 50.560s | 3.801ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.169m | 5.307ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.802m | 35.909ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.111m | 14.583ms | 49 | 50 | 98.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 40.840m | 212.573ms | 41 | 50 | 82.00 |
V3 | TOTAL | 41 | 50 | 82.00 | |||
TOTAL | 1265 | 1290 | 98.06 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 7 | 87.50 |
V2 | 25 | 25 | 14 | 56.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
95.44 | 96.58 | 92.49 | 100.00 | 88.64 | 94.67 | 98.84 | 96.88 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 9 failures:
1.kmac_stress_all_with_rand_reset.8275346580439777043799206617105403487384657846867721608114336032841605385388
Line 672, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18059756853 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
UVM_INFO @ 18059756853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.kmac_stress_all_with_rand_reset.31329599327637085079035265450028997237285704759921502059728604744423274128295
Line 738, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31271462231 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
UVM_INFO @ 31271462231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 4 failures:
Test kmac_key_error has 1 failures.
5.kmac_key_error.92057563519418687868497395224663726026017510069518320147924082272678017479475
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_key_error/latest/run.log
Job ID: smart:15ed8d77-1a0b-4051-87c8-fefdccf6060c
Test kmac_stress_all has 1 failures.
33.kmac_stress_all.110786346459667432821980234446860192921968343763812778914859314170427198524254
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest/run.log
Job ID: smart:98440cbc-6213-482a-aa2e-0634f438200d
Test kmac_sideload has 1 failures.
41.kmac_sideload.58574199000591955789684603146352599036168470337321954216697824085749635784354
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_sideload/latest/run.log
Job ID: smart:ecaf0632-6052-4919-ad61-8d7fd2fa9958
Test kmac_test_vectors_kmac_xof has 1 failures.
49.kmac_test_vectors_kmac_xof.50483152506812717390952054032471524734643551683617897576664876696193819411445
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_test_vectors_kmac_xof/latest/run.log
Job ID: smart:9cec3899-18ca-4d7d-b546-eaad4e205eb5
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 3 failures:
Test kmac_burst_write has 2 failures.
0.kmac_burst_write.57751705114662398188000696036656529517816871392904712996279972027950758461438
Line 365, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.kmac_burst_write.109035343671811923076385777344047295788568493885837930229229442482696727438273
Line 341, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
33.kmac_error.62354715237522374065376231046421802906278570443010264536921396709712537495157
Line 419, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 3 failures:
Test kmac_app_with_partial_data has 1 failures.
3.kmac_app_with_partial_data.100852014790181483131493362736839962184066458468263543791716422580860831127450
Line 281, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 15746237623 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (6 [0x6] vs 27 [0x1b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 15746237623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
35.kmac_entropy_refresh.54300526489432264713681010154458425381249713429531988728197005110949243343792
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 2930268681 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (242 [0xf2] vs 243 [0xf3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 2930268681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
46.kmac_stress_all.42136160330341019728293498524289599080711368762464430343750674739628613088487
Line 285, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_stress_all/latest/run.log
UVM_FATAL @ 7126353265 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 79 [0x4f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 7126353265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 3 failures:
Test kmac_test_vectors_kmac has 1 failures.
24.kmac_test_vectors_kmac.29819330240667289894544962590581626600259362189703427265910672796019260776008
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_test_vectors_kmac/latest/run.log
Job ID: smart:1a252827-be44-4dd3-a187-a3f7ef9649f1
Test kmac_smoke has 1 failures.
25.kmac_smoke.49917298092822611747637157901800453543742518917525449531980974692116479587540
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_smoke/latest/run.log
Job ID: smart:bfbc8f89-c14d-4ac4-ab4b-c5d25f999ef4
Test kmac_test_vectors_sha3_224 has 1 failures.
35.kmac_test_vectors_sha3_224.84368983337273192657884993245722374736983876423995737954326846163554293229820
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:bf2f5b07-f2f7-4d37-8e14-2178faeb6c8f
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 2 failures:
Test kmac_burst_write has 1 failures.
1.kmac_burst_write.51804470867533731545993852228009493699075716651530508961224192420730554572622
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest/run.log
Job ID: smart:1a058131-3896-4bd9-b552-fc6bc7d277c6
Test kmac_alert_test has 1 failures.
18.kmac_alert_test.17994855345006257198419406573715402787661067375083976073245562321111587956453
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_alert_test/latest/run.log
Job ID: smart:d6e2b7ff-9d59-405c-8141-24330559f002
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *]
has 1 failures:
26.kmac_test_vectors_kmac_xof.39126629916322662815752468850105962646480765757153413978772155724311363689271
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_test_vectors_kmac_xof/latest/run.log
Job ID: smart:08f20e95-8b49-4bf2-a028-01cf26ffde29