KMAC/UNMASKED Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.111m 14.583ms 49 50 98.00
V1 csr_hw_reset kmac_csr_hw_reset 1.170s 118.454us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.210s 62.116us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 20.080s 4.304ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 11.660s 2.218ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.450s 55.566us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.210s 62.116us 20 20 100.00
kmac_csr_aliasing 11.660s 2.218ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.740s 15.231us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.580s 139.641us 5 5 100.00
V1 TOTAL 114 115 99.13
V2 long_msg_and_output kmac_long_msg_and_output 50.713m 158.051ms 50 50 100.00
V2 burst_write kmac_burst_write 15.837m 159.761ms 47 50 94.00
V2 test_vectors kmac_test_vectors_sha3_224 35.749m 101.668ms 49 50 98.00
kmac_test_vectors_sha3_256 34.256m 255.652ms 50 50 100.00
kmac_test_vectors_sha3_384 24.855m 94.365ms 50 50 100.00
kmac_test_vectors_sha3_512 17.631m 50.491ms 50 50 100.00
kmac_test_vectors_shake_128 1.502h 1.077s 50 50 100.00
kmac_test_vectors_shake_256 1.279h 913.128ms 50 50 100.00
kmac_test_vectors_kmac 5.550s 988.130us 49 50 98.00
kmac_test_vectors_kmac_xof 5.670s 2.067ms 48 50 96.00
V2 sideload kmac_sideload 6.521m 39.523ms 49 50 98.00
V2 app kmac_app 5.458m 52.500ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 5.609m 116.510ms 9 10 90.00
V2 entropy_refresh kmac_entropy_refresh 5.174m 14.390ms 49 50 98.00
V2 error kmac_error 8.188m 117.733ms 49 50 98.00
V2 key_error kmac_key_error 7.090s 12.567ms 49 50 98.00
V2 edn_timeout_error kmac_edn_timeout_error 38.610s 4.048ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 37.500s 3.910ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.046m 13.992ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 50.560s 3.801ms 50 50 100.00
V2 stress_all kmac_stress_all 37.602m 323.143ms 48 50 96.00
V2 intr_test kmac_intr_test 0.850s 18.333us 50 50 100.00
V2 alert_test kmac_alert_test 0.900s 201.320us 49 50 98.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.840s 1.141ms 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.840s 1.141ms 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.170s 118.454us 5 5 100.00
kmac_csr_rw 1.210s 62.116us 20 20 100.00
kmac_csr_aliasing 11.660s 2.218ms 5 5 100.00
kmac_same_csr_outstanding 3.160s 1.701ms 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.170s 118.454us 5 5 100.00
kmac_csr_rw 1.210s 62.116us 20 20 100.00
kmac_csr_aliasing 11.660s 2.218ms 5 5 100.00
kmac_same_csr_outstanding 3.160s 1.701ms 20 20 100.00
V2 TOTAL 1035 1050 98.57
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.420s 62.389us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.420s 62.389us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.420s 62.389us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.420s 62.389us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.120s 1.203ms 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.169m 5.307ms 5 5 100.00
kmac_tl_intg_err 5.800s 324.519us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.800s 324.519us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 50.560s 3.801ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.111m 14.583ms 49 50 98.00
V2S sec_cm_key_sideload kmac_sideload 6.521m 39.523ms 49 50 98.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.420s 62.389us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.169m 5.307ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.169m 5.307ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.169m 5.307ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.111m 14.583ms 49 50 98.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 50.560s 3.801ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.169m 5.307ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.802m 35.909ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.111m 14.583ms 49 50 98.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 40.840m 212.573ms 41 50 82.00
V3 TOTAL 41 50 82.00
TOTAL 1265 1290 98.06

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 25 25 14 56.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.44 96.58 92.49 100.00 88.64 94.67 98.84 96.88

Failure Buckets

Past Results