KMAC/UNMASKED Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.099m	15.107ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.050s	52.213us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	145.174us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.720s	304.361us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.710s	1.039ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.610s	136.900us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	145.174us	20	20	100.00
		kmac_csr_aliasing	5.710s	1.039ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	14.013us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	75.983us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.586m	539.896ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.588m	71.978ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.762m	450.575ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.113m	188.059ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.549m	783.207ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.105m	226.120ms	50	50	100.00
		kmac_test_vectors_shake_128	1.577h	1.912s	50	50	100.00
		kmac_test_vectors_shake_256	1.365h	902.575ms	50	50	100.00
		kmac_test_vectors_kmac	5.460s	670.619us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.670s	502.128us	50	50	100.00
V2	sideload	kmac_sideload	7.413m	74.797ms	50	50	100.00
V2	app	kmac_app	5.251m	66.855ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.030m	34.620ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.682m	84.068ms	50	50	100.00
V2	error	kmac_error	7.291m	77.879ms	50	50	100.00
V2	key_error	kmac_key_error	9.430s	17.729ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.780s	1.843ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.170s	1.615ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.058m	15.117ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	35.650s	2.980ms	50	50	100.00
V2	stress_all	kmac_stress_all	41.488m	31.836ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.860s	33.359us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	32.979us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.690s	126.346us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.690s	126.346us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.050s	52.213us	5	5	100.00
		kmac_csr_rw	1.210s	145.174us	20	20	100.00
		kmac_csr_aliasing	5.710s	1.039ms	5	5	100.00
		kmac_same_csr_outstanding	2.800s	126.918us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.050s	52.213us	5	5	100.00
		kmac_csr_rw	1.210s	145.174us	20	20	100.00
		kmac_csr_aliasing	5.710s	1.039ms	5	5	100.00
		kmac_same_csr_outstanding	2.800s	126.918us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	138.812us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	138.812us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	138.812us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	138.812us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.860s	415.084us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	58.290s	16.385ms	5	5	100.00
		kmac_tl_intg_err	5.400s	249.694us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.400s	249.694us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	35.650s	2.980ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.099m	15.107ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.413m	74.797ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	138.812us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	58.290s	16.385ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	58.290s	16.385ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	58.290s	16.385ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.099m	15.107ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	35.650s	2.980ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	58.290s	16.385ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.236m	56.014ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.099m	15.107ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.201m	214.581ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			1244	1290	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.33	96.18	92.38	100.00	88.64	94.52	98.84	96.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 0.kmac_stress_all_with_rand_reset.3744116311161484779950521455301996742452585088749036847372764141198531821574
    Line 614, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70759942710 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 70759942710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.27311156260053270955689121235005423982012513252005535771573312905903798031287
    Line 687, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45315662204 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 45315662204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 8.kmac_stress_all_with_rand_reset.102613356453057755607779635720407230572808928901951431052560515704166809480650
    Line 358, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 460107352 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 460107352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.84133124692608177216598279978904438402918232568787889855454217138231036701432
    Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 722641338 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 722641338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_burst_write has 3 failures.
  - 9.kmac_burst_write.70952725002032331238126012004127522582212704660277205686810318728061244480735
    Line 818, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.kmac_burst_write.97814813694556313134734282340289120971647603906016191927790177853712767713379
    Line 632, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 2 failures:

Test kmac_app has 2 failures.

0.kmac_app.63651652176179730804748581589841281303826985712953095572452946188252659183544
Line 387, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app/latest/run.log

  UVM_FATAL @ 641358808 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (70 [0x46] vs 183 [0xb7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 641358808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_app.113887235827854860068341798970191957866537370458664092449844010250050514857801
Line 927, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_app/latest/run.log

  UVM_FATAL @ 37842409998 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 37842409998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---