KMAC/UNMASKED Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.111m	4.050ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	113.631us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	28.197us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.800s	1.228ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.040s	2.408ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.690s	66.052us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	28.197us	20	20	100.00
		kmac_csr_aliasing	10.040s	2.408ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	38.227us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	41.145us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.748m	388.126ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.046m	27.486ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.376m	514.341ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.099m	97.281ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.122m	378.298ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.323m	805.789ms	50	50	100.00
		kmac_test_vectors_shake_128	1.542h	1.031s	50	50	100.00
		kmac_test_vectors_shake_256	1.471h	3.101s	50	50	100.00
		kmac_test_vectors_kmac	5.780s	2.089ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.810s	1.580ms	50	50	100.00
V2	sideload	kmac_sideload	7.717m	100.239ms	49	50	98.00
V2	app	kmac_app	5.384m	67.110ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.255m	35.979ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.415m	16.225ms	50	50	100.00
V2	error	kmac_error	6.374m	17.338ms	50	50	100.00
V2	key_error	kmac_key_error	8.340s	5.088ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.020s	9.316ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.860s	1.257ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.587m	91.635ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.010s	3.491ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.662m	443.761ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	18.326us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	82.517us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.480s	548.900us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.480s	548.900us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	113.631us	5	5	100.00
		kmac_csr_rw	1.190s	28.197us	20	20	100.00
		kmac_csr_aliasing	10.040s	2.408ms	5	5	100.00
		kmac_same_csr_outstanding	2.500s	446.293us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	113.631us	5	5	100.00
		kmac_csr_rw	1.190s	28.197us	20	20	100.00
		kmac_csr_aliasing	10.040s	2.408ms	5	5	100.00
		kmac_same_csr_outstanding	2.500s	446.293us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	47.320us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	47.320us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	47.320us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	47.320us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.070s	128.897us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.276m	17.876ms	5	5	100.00
		kmac_tl_intg_err	5.460s	1.493ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.460s	1.493ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.010s	3.491ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.111m	4.050ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.717m	100.239ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	47.320us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.276m	17.876ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.276m	17.876ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.276m	17.876ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.111m	4.050ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.010s	3.491ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.276m	17.876ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.935m	57.833ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.111m	4.050ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.312m	82.007ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1247	1290	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.64	96.18	92.38	100.00	84.09	94.52	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 1.kmac_stress_all_with_rand_reset.90862652450227702873590172566334266684058955313157983323535470683709159632440
    Line 342, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9385849518 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9385849518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.83654836822609148040699287946370460162333437372067823045705868692180261256615
    Line 442, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50949425123 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50949425123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 11.kmac_stress_all_with_rand_reset.8184150669769593859014586130802377217802827501603047426637988530532363443593
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  45801343 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @  45801343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.63874060736832720634658438883439770388191566339474279183391071615640357960316
    Line 719, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15888793430 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 15888793430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_app_with_partial_data has 1 failures.

5.kmac_app_with_partial_data.24308214742323773038763611867849542661624975309439562505050180932456710502880
Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 4131788889 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (54 [0x36] vs 216 [0xd8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4131788889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

5.kmac_stress_all.11699074522298892235271959458424437610836051854253390300997060827585668896219
Line 1215, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all/latest/run.log

  UVM_FATAL @ 26708806088 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (230 [0xe6] vs 239 [0xef]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 26708806088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

7.kmac_mubi.22586147712289617811772299310179555374992213988102459737680357855734402251400
Line 749, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_mubi/latest/run.log

  UVM_FATAL @ 6508019199 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (122 [0x7a] vs 168 [0xa8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6508019199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_sideload has 1 failures.
  - 39.kmac_sideload.55316838991177679033337295631971880937391986436412532428193390836454121459503
    Line 1077, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```