KMAC/UNMASKED Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 0 50 0.00
V1 csr_hw_reset kmac_csr_hw_reset 1.230s 390.744us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.180s 113.963us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 17.980s 3.847ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 9.820s 600.995us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.610s 127.226us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.180s 113.963us 20 20 100.00
kmac_csr_aliasing 9.820s 600.995us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.770s 30.442us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.550s 148.888us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 long_msg_and_output kmac_long_msg_and_output 0 50 0.00
V2 burst_write kmac_burst_write 0 50 0.00
V2 test_vectors kmac_test_vectors_sha3_224 0 50 0.00
kmac_test_vectors_sha3_256 0 50 0.00
kmac_test_vectors_sha3_384 0 50 0.00
kmac_test_vectors_sha3_512 0 50 0.00
kmac_test_vectors_shake_128 0 50 0.00
kmac_test_vectors_shake_256 0 50 0.00
kmac_test_vectors_kmac 0 50 0.00
kmac_test_vectors_kmac_xof 0 50 0.00
V2 sideload kmac_sideload 0 50 0.00
V2 app kmac_app 0 50 0.00
V2 app_with_partial_data kmac_app_with_partial_data 0 10 0.00
V2 entropy_refresh kmac_entropy_refresh 0 50 0.00
V2 error kmac_error 0 50 0.00
V2 key_error kmac_key_error 0 50 0.00
V2 edn_timeout_error kmac_edn_timeout_error 0 20 0.00
V2 entropy_mode_error kmac_entropy_mode_error 0 20 0.00
V2 entropy_ready_error kmac_entropy_ready_error 0 10 0.00
V2 lc_escalation kmac_lc_escalation 0 50 0.00
V2 stress_all kmac_stress_all 0 50 0.00
V2 intr_test kmac_intr_test 0.910s 11.266us 50 50 100.00
V2 alert_test kmac_alert_test 0 50 0.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.080s 686.100us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.080s 686.100us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.230s 390.744us 5 5 100.00
kmac_csr_rw 1.180s 113.963us 20 20 100.00
kmac_csr_aliasing 9.820s 600.995us 5 5 100.00
kmac_same_csr_outstanding 2.910s 622.609us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.230s 390.744us 5 5 100.00
kmac_csr_rw 1.180s 113.963us 20 20 100.00
kmac_csr_aliasing 9.820s 600.995us 5 5 100.00
kmac_same_csr_outstanding 2.910s 622.609us 20 20 100.00
V2 TOTAL 90 1050 8.57
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.450s 65.728us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.450s 65.728us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.450s 65.728us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.450s 65.728us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.190s 178.901us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 0 5 0.00
kmac_tl_intg_err 4.920s 626.734us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.920s 626.734us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 0 50 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 0 50 0.00
V2S sec_cm_key_sideload kmac_sideload 0 50 0.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.450s 65.728us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 0 5 0.00
V2S sec_cm_ctr_redun kmac_sec_cm 0 5 0.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 0 5 0.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 0 50 0.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 0 50 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 0 5 0.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 0 10 0.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 0 50 0.00
V2S TOTAL 60 75 80.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 215 1290 16.67

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 25 25 3 12.00
V2S 5 5 3 60.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
48.45 48.31 64.41 16.56 0.00 48.00 100.00 61.84

Failure Buckets

Past Results