KMAC/UNMASKED Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.118m	16.526ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	48.278us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.140s	31.869us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.700s	962.186us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.050s	2.083ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	98.051us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.140s	31.869us	20	20	100.00
		kmac_csr_aliasing	10.050s	2.083ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	43.093us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	21.559us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	46.958m	264.883ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.136m	90.825ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.787m	101.634ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.044m	352.627ms	50	50	100.00
		kmac_test_vectors_sha3_384	28.269m	773.435ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.307m	558.594ms	50	50	100.00
		kmac_test_vectors_shake_128	1.708h	2.310s	50	50	100.00
		kmac_test_vectors_shake_256	1.458h	2.708s	50	50	100.00
		kmac_test_vectors_kmac	5.390s	2.600ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.470s	1.053ms	50	50	100.00
V2	sideload	kmac_sideload	7.521m	30.750ms	50	50	100.00
V2	app	kmac_app	5.236m	24.813ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.850m	9.282ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.380m	83.570ms	49	50	98.00
V2	error	kmac_error	7.048m	21.345ms	48	50	96.00
V2	key_error	kmac_key_error	7.210s	7.147ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.890s	7.175ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.980s	3.003ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.780s	10.780ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.880s	978.427us	50	50	100.00
V2	stress_all	kmac_stress_all	42.755m	95.850ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	16.716us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	86.774us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	2.119ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	2.119ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	48.278us	5	5	100.00
		kmac_csr_rw	1.140s	31.869us	20	20	100.00
		kmac_csr_aliasing	10.050s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	2.460s	370.575us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	48.278us	5	5	100.00
		kmac_csr_rw	1.140s	31.869us	20	20	100.00
		kmac_csr_aliasing	10.050s	2.083ms	5	5	100.00
		kmac_same_csr_outstanding	2.460s	370.575us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.320s	73.350us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.320s	73.350us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.320s	73.350us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.320s	73.350us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.100s	138.444us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	59.330s	13.009ms	5	5	100.00
		kmac_tl_intg_err	5.210s	591.885us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.210s	591.885us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.880s	978.427us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.118m	16.526ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.521m	30.750ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.320s	73.350us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.330s	13.009ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.330s	13.009ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.330s	13.009ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.118m	16.526ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.880s	978.427us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.330s	13.009ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.194m	11.871ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.118m	16.526ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	45.242m	290.344ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.31	96.18	92.38	100.00	88.64	94.52	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 0.kmac_stress_all_with_rand_reset.108740868136207500961962881044409202437314282521254355463484136569145697834517
    Line 1043, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 128481003022 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 128481003022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.96019161079676421011671295509169833072250370614987214838477635674459191311365
    Line 809, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15535479848 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15535479848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 10.kmac_stress_all_with_rand_reset.86352381496501058979707476801931836493913169877440213726158572166526183571591
    Line 652, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39329824870 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 39329824870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_stress_all_with_rand_reset.34320582008910298037274111385172066927240706660039861351000159900374945295353
    Line 2153, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 78009171898 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 78009171898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 1 failures.

3.kmac_stress_all.97152389059862767034138566268766521543910360311933301805388068723986768180918
Line 787, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all/latest/run.log

  UVM_FATAL @ 49270814131 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (19 [0x13] vs 198 [0xc6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 49270814131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

23.kmac_entropy_refresh.18870906984147236394582851248936384185788821481866557962389654090272654190274
Line 973, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 53144030874 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 210 [0xd2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 53144030874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

25.kmac_error.49080893947492184695625161132714378066039040202087226841347058838819816690978
Line 359, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_error/latest/run.log

  UVM_FATAL @ 6623134866 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (105 [0x69] vs 200 [0xc8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6623134866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

35.kmac_app.78118666280018111736142177789810512317603023124193511898805463081718205308379
Line 387, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_app/latest/run.log

  UVM_FATAL @ 5788209664 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 8 [0x8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5788209664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 1 failures.
  - 19.kmac_error.98268202822842299387662713049980859054573384464051995886798044061916987322580
    Line 1047, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app has 1 failures.
  - 25.kmac_app.55530114940403214308397776534850110917471000505763536001247506247589858264512
    Line 775, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```