KMAC/UNMASKED Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: `b111fbcef3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.147m	33.270ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.000s	31.397us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.150s	26.080us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.260s	3.576ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.640s	544.779us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.830s	95.332us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.150s	26.080us	20	20	100.00
		kmac_csr_aliasing	10.640s	544.779us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	27.717us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	40.776us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.053m	256.159ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.082m	18.879ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.642m	727.987ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.909m	387.129ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.518m	437.927ms	50	50	100.00
		kmac_test_vectors_sha3_512	21.325m	815.064ms	50	50	100.00
		kmac_test_vectors_shake_128	1.587h	1.083s	50	50	100.00
		kmac_test_vectors_shake_256	1.238h	219.452ms	50	50	100.00
		kmac_test_vectors_kmac	5.410s	1.102ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.230s	3.107ms	50	50	100.00
V2	sideload	kmac_sideload	7.225m	82.192ms	50	50	100.00
V2	app	kmac_app	5.104m	67.794ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.062m	123.750ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.592m	21.699ms	49	50	98.00
V2	error	kmac_error	6.801m	78.727ms	50	50	100.00
V2	key_error	kmac_key_error	8.710s	6.735ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.700s	1.676ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.250s	6.130ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.890s	24.747ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.290s	833.567us	50	50	100.00
V2	stress_all	kmac_stress_all	31.427m	155.913ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.840s	19.848us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	33.523us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.880s	155.798us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.880s	155.798us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.000s	31.397us	5	5	100.00
		kmac_csr_rw	1.150s	26.080us	20	20	100.00
		kmac_csr_aliasing	10.640s	544.779us	5	5	100.00
		kmac_same_csr_outstanding	2.990s	488.662us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.000s	31.397us	5	5	100.00
		kmac_csr_rw	1.150s	26.080us	20	20	100.00
		kmac_csr_aliasing	10.640s	544.779us	5	5	100.00
		kmac_same_csr_outstanding	2.990s	488.662us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.610s	82.942us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.610s	82.942us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.610s	82.942us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.610s	82.942us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.950s	219.542us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.213m	26.576ms	5	5	100.00
		kmac_tl_intg_err	5.120s	937.771us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.120s	937.771us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.290s	833.567us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.147m	33.270ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.225m	82.192ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.610s	82.942us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.213m	26.576ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.213m	26.576ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.213m	26.576ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.147m	33.270ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.290s	833.567us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.213m	26.576ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.036m	4.289ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.147m	33.270ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	45.757m	673.343ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1247	1290	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.42	96.18	92.17	100.00	89.77	94.52	98.84	96.45

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test kmac_stress_all_with_rand_reset has 32 failures.
  - 0.kmac_stress_all_with_rand_reset.96163308859276059727096276043253086838992295112400026744820840650549590539012
    Line 848, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11532787505 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11532787505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.60083013903258530272428781023025030792015064202438801346809664227606783963427
    Line 1160, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28539498424 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28539498424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 13.kmac_stress_all_with_rand_reset.55800974751973145201985262935802520610834912537515790622875290545713752680372
    Line 1671, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 338500697040 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 338500697040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.kmac_stress_all_with_rand_reset.78266583696769435271889244666329789741493928340286941998213144063304675078649
    Line 973, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11388284891 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 11388284891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.58553844905837666358296559701757726720770763719193238866723646094858112592319
Line 637, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 48649826856 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (171 [0xab] vs 117 [0x75]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 48649826856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

26.kmac_app.38977846442246774308316752169343968548573417486945666207239976290310292635392
Line 369, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_app/latest/run.log

  UVM_FATAL @ 1844015737 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (91 [0x5b] vs 126 [0x7e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1844015737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.kmac_app.42068067929017068962083011669906093943112952557940273532089075376306875167026
Line 857, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_app/latest/run.log

  UVM_FATAL @ 14183628360 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (107 [0x6b] vs 135 [0x87]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14183628360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 11.kmac_entropy_refresh.71521877640048562732196402117939249918038806561315743708832495688793586572051
    Line 1094, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 17.kmac_burst_write.12416377252340310300611162174359287701957173956372093924459820383256834908757
    Line 800, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```