KMAC/UNMASKED Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.148m	18.241ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.070s	22.121us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	142.706us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.630s	6.026ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.000s	466.599us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.660s	77.197us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	142.706us	20	20	100.00
		kmac_csr_aliasing	9.000s	466.599us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	13.074us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	81.101us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.637m	132.003ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.786m	35.699ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.824m	205.313ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.172m	684.136ms	50	50	100.00
		kmac_test_vectors_sha3_384	29.572m	715.693ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.865m	815.228ms	50	50	100.00
		kmac_test_vectors_shake_128	1.598h	1.077s	50	50	100.00
		kmac_test_vectors_shake_256	1.325h	875.848ms	50	50	100.00
		kmac_test_vectors_kmac	5.550s	1.036ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.810s	1.006ms	50	50	100.00
V2	sideload	kmac_sideload	7.300m	19.458ms	50	50	100.00
V2	app	kmac_app	5.861m	53.061ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.844m	49.186ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.788m	200.000ms	48	50	96.00
V2	error	kmac_error	6.813m	46.597ms	50	50	100.00
V2	key_error	kmac_key_error	8.060s	10.045ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.870s	1.560ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.400s	6.828ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.955m	155.240ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.660s	1.137ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.759m	289.853ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.880s	17.714us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	33.208us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.240s	186.038us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.240s	186.038us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.070s	22.121us	5	5	100.00
		kmac_csr_rw	1.200s	142.706us	20	20	100.00
		kmac_csr_aliasing	9.000s	466.599us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	1.452ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.070s	22.121us	5	5	100.00
		kmac_csr_rw	1.200s	142.706us	20	20	100.00
		kmac_csr_aliasing	9.000s	466.599us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	1.452ms	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	45.716us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	45.716us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	45.716us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	45.716us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.260s	219.820us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	49.720s	38.919ms	5	5	100.00
		kmac_tl_intg_err	5.530s	1.265ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.530s	1.265ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.660s	1.137ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.148m	18.241ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.300m	19.458ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	45.716us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	49.720s	38.919ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	49.720s	38.919ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	49.720s	38.919ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.148m	18.241ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.660s	1.137ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	49.720s	38.919ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.571m	25.875ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.148m	18.241ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.935m	73.776ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1245	1290	96.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	96.18	92.13	100.00	90.91	94.52	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 0.kmac_stress_all_with_rand_reset.101415003444140200229042879383215027552001994326827137285068945517550656561483
    Line 380, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2283888273 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2283888273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.43077472096635855010269255155664847240570862375723176528844520494667935453722
    Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4615940747 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4615940747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test kmac_app has 2 failures.

13.kmac_app.44459926569434043178568811735785983087717787370608894636380619786306867438309
Line 764, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_app/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.kmac_app.93901244527602702402522598904829430263967477322138733237852654540353641840458
Line 845, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_app/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.
- 15.kmac_entropy_refresh.67885232889615418444237294766830216101568669566241923519627913231867857029658
  Line 1047, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test kmac_burst_write has 2 failures.

36.kmac_burst_write.33894364536197200059762764874341561437431980876274363454820076605910844192645
Line 638, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_burst_write.55215267473291698970325338790861632576196139984444789386278527071874553134090
Line 1088, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 16.kmac_stress_all.74507201509045704174737833731585061642124360436444833194330844635121468096068
    Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 2002056635 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (33 [0x21] vs 22 [0x16]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2002056635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 26.kmac_entropy_refresh.15554968523731878471621793931058688303379094688944482253983001594892056830798
    Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 1238196727 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (227 [0xe3] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1238196727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 35.kmac_stress_all_with_rand_reset.21058641617154509138553388617834558784045166036044332268864738051952602145748
    Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 45761122105 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (184 [0xb8] vs 71 [0x47]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 45761122105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 15.kmac_stress_all_with_rand_reset.32294529258113701860053025765484986340498353103516172310663434891836033022169
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 285099196 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 285099196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```