KMAC/UNMASKED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.070m 4.173ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.030s 52.370us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.250s 31.007us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 18.760s 1.997ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.810s 4.511ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.520s 138.799us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.250s 31.007us 20 20 100.00
kmac_csr_aliasing 10.810s 4.511ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.790s 68.896us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.440s 145.854us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 49.271m 474.999ms 50 50 100.00
V2 burst_write kmac_burst_write 13.037m 67.222ms 49 50 98.00
V2 test_vectors kmac_test_vectors_sha3_224 34.755m 203.028ms 50 50 100.00
kmac_test_vectors_sha3_256 35.468m 380.115ms 50 50 100.00
kmac_test_vectors_sha3_384 25.808m 428.466ms 50 50 100.00
kmac_test_vectors_sha3_512 20.570m 714.037ms 50 50 100.00
kmac_test_vectors_shake_128 1.591h 2.108s 50 50 100.00
kmac_test_vectors_shake_256 1.325h 2.092s 50 50 100.00
kmac_test_vectors_kmac 5.300s 231.904us 50 50 100.00
kmac_test_vectors_kmac_xof 5.710s 1.003ms 50 50 100.00
V2 sideload kmac_sideload 6.870m 20.084ms 50 50 100.00
V2 app kmac_app 6.340m 36.510ms 47 50 94.00
V2 app_with_partial_data kmac_app_with_partial_data 5.445m 16.130ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 5.450m 14.047ms 47 50 94.00
V2 error kmac_error 6.932m 40.590ms 50 50 100.00
V2 key_error kmac_key_error 13.210s 19.113ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 46.250s 6.879ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 30.590s 1.683ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 58.070s 6.856ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 37.550s 837.154us 50 50 100.00
V2 stress_all kmac_stress_all 37.566m 81.356ms 50 50 100.00
V2 intr_test kmac_intr_test 0.850s 27.867us 50 50 100.00
V2 alert_test kmac_alert_test 0.860s 16.043us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.230s 419.440us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.230s 419.440us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.030s 52.370us 5 5 100.00
kmac_csr_rw 1.250s 31.007us 20 20 100.00
kmac_csr_aliasing 10.810s 4.511ms 5 5 100.00
kmac_same_csr_outstanding 2.780s 127.982us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.030s 52.370us 5 5 100.00
kmac_csr_rw 1.250s 31.007us 20 20 100.00
kmac_csr_aliasing 10.810s 4.511ms 5 5 100.00
kmac_same_csr_outstanding 2.780s 127.982us 20 20 100.00
V2 TOTAL 1043 1050 99.33
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.440s 139.796us 17 20 85.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.440s 139.796us 17 20 85.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.440s 139.796us 17 20 85.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.440s 139.796us 17 20 85.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.050s 527.858us 18 20 90.00
V2S tl_intg_err kmac_sec_cm 1.327m 50.850ms 5 5 100.00
kmac_tl_intg_err 5.090s 1.320ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.090s 1.320ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 37.550s 837.154us 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.070m 4.173ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 6.870m 20.084ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.440s 139.796us 17 20 85.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.327m 50.850ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.327m 50.850ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.327m 50.850ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.070m 4.173ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 37.550s 837.154us 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.327m 50.850ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 3.315m 200.000ms 9 10 90.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.070m 4.173ms 50 50 100.00
V2S TOTAL 69 75 92.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 51.667m 138.965ms 6 50 12.00
V3 TOTAL 6 50 12.00
TOTAL 1233 1290 95.58

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 22 88.00
V2S 5 5 2 40.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.20 95.88 92.26 100.00 67.77 94.11 98.84 96.58

Failure Buckets

Past Results