KMAC/UNMASKED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.070m	4.173ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	52.370us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	31.007us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.760s	1.997ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.810s	4.511ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.520s	138.799us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	31.007us	20	20	100.00
		kmac_csr_aliasing	10.810s	4.511ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	68.896us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	145.854us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.271m	474.999ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.037m	67.222ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.755m	203.028ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.468m	380.115ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.808m	428.466ms	50	50	100.00
		kmac_test_vectors_sha3_512	20.570m	714.037ms	50	50	100.00
		kmac_test_vectors_shake_128	1.591h	2.108s	50	50	100.00
		kmac_test_vectors_shake_256	1.325h	2.092s	50	50	100.00
		kmac_test_vectors_kmac	5.300s	231.904us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.710s	1.003ms	50	50	100.00
V2	sideload	kmac_sideload	6.870m	20.084ms	50	50	100.00
V2	app	kmac_app	6.340m	36.510ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.445m	16.130ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.450m	14.047ms	47	50	94.00
V2	error	kmac_error	6.932m	40.590ms	50	50	100.00
V2	key_error	kmac_key_error	13.210s	19.113ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.250s	6.879ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.590s	1.683ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.070s	6.856ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.550s	837.154us	50	50	100.00
V2	stress_all	kmac_stress_all	37.566m	81.356ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	27.867us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	16.043us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.230s	419.440us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.230s	419.440us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	52.370us	5	5	100.00
		kmac_csr_rw	1.250s	31.007us	20	20	100.00
		kmac_csr_aliasing	10.810s	4.511ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	127.982us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	52.370us	5	5	100.00
		kmac_csr_rw	1.250s	31.007us	20	20	100.00
		kmac_csr_aliasing	10.810s	4.511ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	127.982us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	139.796us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	139.796us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	139.796us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	139.796us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	527.858us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.327m	50.850ms	5	5	100.00
		kmac_tl_intg_err	5.090s	1.320ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.090s	1.320ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.550s	837.154us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.070m	4.173ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.870m	20.084ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	139.796us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.327m	50.850ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.327m	50.850ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.327m	50.850ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.070m	4.173ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.550s	837.154us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.327m	50.850ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.315m	200.000ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.070m	4.173ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.667m	138.965ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			1233	1290	95.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.20	95.88	92.26	100.00	67.77	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test kmac_stress_all_with_rand_reset has 36 failures.
  - 0.kmac_stress_all_with_rand_reset.88463712099729722091915669770110573236611793368193450761772292454250597635100
    Line 1304, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63524008135 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 63524008135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.56461597596870218032708716720484706498066363524658114081927577601356219077424
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 122281489 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 122281489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 4.kmac_stress_all_with_rand_reset.108569888226386819660315007816189435105633232244991337774234531021504270953522
    Line 885, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103318469707 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 103318469707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.24217367062045760958556403039765755331180477803211331585169557709768959176597
    Line 594, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9755087733 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9755087733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

2.kmac_shadow_reg_errors_with_csr_rw.36875905038000117780749434110686745029209067582401989877232044691107342016636
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  69809730 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  69809730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.76320876428675138665728497340123103964150769089992035701975527017395072362646
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 166793494 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 166793494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 3 failures.

6.kmac_shadow_reg_errors.68413273809236002610339990758479657037372260064240901368813599243938673119483
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  28466296 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  28466296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors.3979084030753797327563679887971441851383921833025630922272239219068780630998
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  10016406 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10016406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 3 failures.

4.kmac_app.68165968309443574779384497961031665820434830371316138556383508386902192817637
Line 385, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_app/latest/run.log

  UVM_FATAL @ 4949282086 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 17 [0x11]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4949282086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_app.107822902321528903216547125039851536358648237917440399021088376401700364533158
Line 509, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 7197975119 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (161 [0xa1] vs 157 [0x9d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7197975119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 2 failures.

17.kmac_entropy_refresh.1479521536977314110427397477466453174369648022696348227766144920224218754743
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 315952493 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (147 [0x93] vs 183 [0xb7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 315952493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.kmac_entropy_refresh.27729563386399187438375545027917150660795130125307818030292675549334467051905
Line 771, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 180951639526 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (89 [0x59] vs 59 [0x3b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 180951639526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 8.kmac_entropy_refresh.90696449193582220582215855726963608057458409736432738271194549290547718433378
    Line 1036, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_mubi has 1 failures.
  - 8.kmac_mubi.96402091924141885049844211041222125509068718939252620272562468205532517930638
    Line 896, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 31.kmac_burst_write.102140326115064002154968230754816799327676452626071637980127923780991740754234
    Line 824, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```