KMAC/UNMASKED Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.044m	15.689ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.200s	99.098us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	451.086us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.940s	1.328ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.260s	966.317us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	137.980us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	451.086us	20	20	100.00
		kmac_csr_aliasing	10.260s	966.317us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	13.669us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	68.654us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.025m	367.058ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.317m	131.041ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.454m	1.092s	50	50	100.00
		kmac_test_vectors_sha3_256	32.658m	508.509ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.009m	298.021ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.355m	409.377ms	50	50	100.00
		kmac_test_vectors_shake_128	1.826h	4.274s	50	50	100.00
		kmac_test_vectors_shake_256	1.291h	853.192ms	50	50	100.00
		kmac_test_vectors_kmac	5.370s	935.024us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.680s	1.452ms	50	50	100.00
V2	sideload	kmac_sideload	9.559m	417.894ms	50	50	100.00
V2	app	kmac_app	5.966m	104.363ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.165m	15.428ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.202m	40.629ms	48	50	96.00
V2	error	kmac_error	6.410m	19.428ms	50	50	100.00
V2	key_error	kmac_key_error	9.540s	1.977ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.310s	2.266ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.160s	2.241ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.393m	63.142ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.920s	4.382ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.030m	74.141ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	18.864us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	112.423us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.280s	106.744us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.280s	106.744us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.200s	99.098us	5	5	100.00
		kmac_csr_rw	1.190s	451.086us	20	20	100.00
		kmac_csr_aliasing	10.260s	966.317us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	91.115us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.200s	99.098us	5	5	100.00
		kmac_csr_rw	1.190s	451.086us	20	20	100.00
		kmac_csr_aliasing	10.260s	966.317us	5	5	100.00
		kmac_same_csr_outstanding	2.560s	91.115us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	56.128us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	56.128us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	56.128us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	56.128us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.030s	119.393us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.127m	11.334ms	5	5	100.00
		kmac_tl_intg_err	4.880s	1.124ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.880s	1.124ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.920s	4.382ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.044m	15.689ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.559m	417.894ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	56.128us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.127m	11.334ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.127m	11.334ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.127m	11.334ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.044m	15.689ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.920s	4.382ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.127m	11.334ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.365m	20.628ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.044m	15.689ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.755m	84.790ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.63	95.91	92.34	100.00	70.25	94.19	99.00	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 0.kmac_stress_all_with_rand_reset.73107121047081634935784030097776920361516851071614864736361946822487858538442
    Line 423, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3984551374 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3984551374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.34561815376581889341284593281081738326502826347732888906232325431540928854118
    Line 1685, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66056784901 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 66056784901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_app has 2 failures.

1.kmac_app.78090600599723787251499708998979920804158334557199247533599942301624979931919
Line 679, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 2265818913 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (62 [0x3e] vs 35 [0x23]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2265818913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_app.56315422822211178913294759396569402644508277572338811224804739252438010297481
Line 683, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 2308325355 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (27 [0x1b] vs 24 [0x18]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2308325355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

9.kmac_entropy_refresh.974564643244196881072067790702678153524034675571979405627620708562958420747
Line 419, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2572489114 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (114 [0x72] vs 192 [0xc0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2572489114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.kmac_entropy_refresh.98393629720315140192700320038340723839120872757924342090879127525288844931695
Line 579, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2511430852 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (32 [0x20] vs 221 [0xdd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2511430852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

29.kmac_stress_all_with_rand_reset.62602262548382195472693562261140608380716038696843697571260537864453170642994
Line 455, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 37425309351 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (104 [0x68] vs 166 [0xa6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 37425309351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

33.kmac_stress_all.93058625139933397708425187729828129995935842929566248289867176971273363639129
Line 1367, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest/run.log

  UVM_FATAL @ 35748995380 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 80 [0x50]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 35748995380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

0.kmac_shadow_reg_errors_with_csr_rw.107121161057781857958094296233971740139106740589548443029290757598411325715552
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  22318273 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  22318273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.102956788986948496065104802860859072961387273398484004446327433365643924196456
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 277953371 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 277953371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors has 2 failures.

7.kmac_shadow_reg_errors.101986632380509722498234803692152037316732501361307730274972411269043961391157
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  15581323 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  15581323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors.91735981193056010816974304193304505857484806873445918457956749310619117304871
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   6002470 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6002470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 16.kmac_stress_all_with_rand_reset.79902864839201152502545841823346803188689190819366343583929502357142797004554
    Line 704, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64038021746 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 64038021746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.kmac_stress_all_with_rand_reset.46718964413561963022628624997020929756437180627309583116031299714418475328666
    Line 727, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 77171823910 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 77171823910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.