KMAC/UNMASKED Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.154m	13.212ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.300s	63.075us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	100.045us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.550s	3.073ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.850s	1.097ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.800s	96.951us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	100.045us	20	20	100.00
		kmac_csr_aliasing	9.850s	1.097ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	11.981us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.580s	35.921us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.790m	599.892ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.076m	37.855ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.371m	654.989ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.775m	518.148ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.022m	283.339ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.869m	372.724ms	50	50	100.00
		kmac_test_vectors_shake_128	1.571h	1.024s	50	50	100.00
		kmac_test_vectors_shake_256	1.376h	750.763ms	50	50	100.00
		kmac_test_vectors_kmac	5.280s	1.620ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.380s	508.857us	50	50	100.00
V2	sideload	kmac_sideload	6.519m	72.273ms	50	50	100.00
V2	app	kmac_app	5.768m	91.047ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.627m	76.600ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.400m	32.920ms	50	50	100.00
V2	error	kmac_error	7.235m	84.898ms	50	50	100.00
V2	key_error	kmac_key_error	16.210s	29.472ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.600s	7.870ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.790s	2.097ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.870s	7.591ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.470s	724.414us	50	50	100.00
V2	stress_all	kmac_stress_all	37.791m	1.135s	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	24.525us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	223.145us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.450s	495.970us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.450s	495.970us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.300s	63.075us	5	5	100.00
		kmac_csr_rw	1.170s	100.045us	20	20	100.00
		kmac_csr_aliasing	9.850s	1.097ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	861.505us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.300s	63.075us	5	5	100.00
		kmac_csr_rw	1.170s	100.045us	20	20	100.00
		kmac_csr_aliasing	9.850s	1.097ms	5	5	100.00
		kmac_same_csr_outstanding	2.740s	861.505us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	98.009us	19	20	95.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	98.009us	19	20	95.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	98.009us	19	20	95.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	98.009us	19	20	95.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.110s	134.040us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.274m	67.660ms	5	5	100.00
		kmac_tl_intg_err	5.180s	507.060us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.180s	507.060us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.470s	724.414us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.154m	13.212ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.519m	72.273ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	98.009us	19	20	95.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.274m	67.660ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.274m	67.660ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.274m	67.660ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.154m	13.212ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.470s	724.414us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.274m	67.660ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.939m	25.348ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.154m	13.212ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	33.931m	55.101ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1245	1290	96.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.88	92.34	100.00	68.60	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
- Test kmac_stress_all_with_rand_reset has 32 failures.
  - 0.kmac_stress_all_with_rand_reset.78769112126509764635088765316990386517415636954562078384775035691479398502552
    Line 982, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19145821110 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19145821110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.113783782319325388058842015767478516756361958628202206323224228870701379278339
    Line 1905, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 203801440285 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 203801440285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 30 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 1.kmac_stress_all_with_rand_reset.34620691657955138102921315369688607096003658135098119700043970488467999530907
    Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120505685 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 120505685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.49750763665196284310781916228811183132010421200544243100045507028631452006010
    Line 3935, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45132666003 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 45132666003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

0.kmac_shadow_reg_errors_with_csr_rw.13768712367945841334197945715763456023853817972268938840136274702371569731528
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  86213877 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  86213877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors_with_csr_rw.81931463273800244850078242066623419989449092305812783331134457227871844811284
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  35634720 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  35634720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 1 failures.

17.kmac_shadow_reg_errors.59546040170223562002871643700632503665942924634653783885297147819023438890845
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  10238094 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  10238094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_mubi has 1 failures.
  - 3.kmac_mubi.100292424019544186099843240425105101113660135108724065857451195931749114953162
    Line 563, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 21208550328 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (66 [0x42] vs 251 [0xfb]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21208550328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_app_with_partial_data has 1 failures.
  - 9.kmac_app_with_partial_data.33694517497211514230184487002177792724782805329904504030520640623107446163517
    Line 695, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 3175364724 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (53 [0x35] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3175364724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 15.kmac_burst_write.21412924651122714043971069735320553822777161015098660929020346101930562535201
    Line 735, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```