KMAC/UNMASKED Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.202m	13.843ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	49.942us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	301.164us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.450s	1.514ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.950s	1.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.830s	100.507us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	301.164us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.508ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	10.708us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	42.506us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.223m	136.161ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.248m	77.473ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.909m	795.146ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.018m	885.322ms	50	50	100.00
		kmac_test_vectors_sha3_384	28.890m	1.150s	50	50	100.00
		kmac_test_vectors_sha3_512	18.088m	661.043ms	50	50	100.00
		kmac_test_vectors_shake_128	1.648h	3.257s	50	50	100.00
		kmac_test_vectors_shake_256	1.368h	2.702s	50	50	100.00
		kmac_test_vectors_kmac	5.810s	3.386ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.280s	281.175us	50	50	100.00
V2	sideload	kmac_sideload	6.527m	28.884ms	50	50	100.00
V2	app	kmac_app	6.714m	84.445ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.499m	12.644ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.462m	42.352ms	49	50	98.00
V2	error	kmac_error	7.122m	24.646ms	50	50	100.00
V2	key_error	kmac_key_error	10.940s	9.564ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.080s	2.378ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.560s	2.154ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.045m	28.643ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.150s	1.130ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.460m	124.640ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.840s	29.807us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	25.962us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.770s	1.880ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.770s	1.880ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	49.942us	5	5	100.00
		kmac_csr_rw	1.200s	301.164us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.508ms	5	5	100.00
		kmac_same_csr_outstanding	2.400s	92.822us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	49.942us	5	5	100.00
		kmac_csr_rw	1.200s	301.164us	20	20	100.00
		kmac_csr_aliasing	8.950s	1.508ms	5	5	100.00
		kmac_same_csr_outstanding	2.400s	92.822us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.640s	89.564us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.640s	89.564us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.640s	89.564us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.640s	89.564us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.270s	161.055us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.207m	5.665ms	5	5	100.00
		kmac_tl_intg_err	5.270s	296.055us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	296.055us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.150s	1.130ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.202m	13.843ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.527m	28.884ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.640s	89.564us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.207m	5.665ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.207m	5.665ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.207m	5.665ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.202m	13.843ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.150s	1.130ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.207m	5.665ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.375m	58.359ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.202m	13.843ms	50	50	100.00
V2S		TOTAL			69	75	92.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	25.293m	167.770ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1230	1250	98.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.46	95.89	92.27	100.00	69.42	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 0.kmac_stress_all_with_rand_reset.47969892995517475241535386065191300896079192093972750038102673991655329897138
    Line 394, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4899338520 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4899338520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.53399719000922786375655531653928698566614753229949895847995843720131732824960
    Line 732, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8443279201 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8443279201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 5 failures:

Test kmac_shadow_reg_errors has 3 failures.

4.kmac_shadow_reg_errors.37427465063838518601939799935121099112491394756745134317479385449280400439128
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   6014437 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   6014437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors.21864018789303074803163878960346778540181107134459293826615211359004485135454
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   3724694 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   3724694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

4.kmac_shadow_reg_errors_with_csr_rw.65654557076741753811039395196400234778395417737588698066007785795998648612036
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  27692341 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  27692341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.21824868869498982387506578659686771026015472308514734013967996847275504875814
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 270863732 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 270863732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 1 failures.

5.kmac_app.11760370432695018406174035048190046380616071907347544592626320173929762147880
Line 463, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_app/latest/run.log

  UVM_FATAL @ 1098640531 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (19 [0x13] vs 178 [0xb2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1098640531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

5.kmac_entropy_refresh.24876057314872964872511615912203219006098706740379960133817622574128468613223
Line 585, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 12485848418 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (75 [0x4b] vs 82 [0x52]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 12485848418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

6.kmac_mubi.93473141723071093683032669274826283582868335909289687473348334965845520467562
Line 377, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_mubi/latest/run.log

  UVM_FATAL @ 5997700359 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 21 [0x15]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5997700359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

13.kmac_stress_all.115785247534622829020504040660678172710366849552043474419355278105672672049845
Line 691, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_stress_all/latest/run.log

  UVM_FATAL @ 4807303427 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (228 [0xe4] vs 14 [0xe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4807303427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_stress_all.57095918832901819794877396781079102244941803227069479676182340339079164857555
Line 495, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_FATAL @ 11854272188 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (141 [0x8d] vs 59 [0x3b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 11854272188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_burst_write has 1 failures.
  - 7.kmac_burst_write.59947470862605432464531639506978239570261563104212169697644602412828054762338
    Line 891, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```