KMAC/UNMASKED Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.209m	8.153ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.980s	63.136us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	33.248us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.010s	553.249us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.380s	493.439us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	35.150us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	33.248us	20	20	100.00
		kmac_csr_aliasing	9.380s	493.439us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	13.451us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.580s	499.778us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.346m	142.144ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.631m	38.746ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.188m	733.740ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.565m	1.317s	50	50	100.00
		kmac_test_vectors_sha3_384	24.878m	764.966ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.476m	343.318ms	50	50	100.00
		kmac_test_vectors_shake_128	1.562h	1.176s	50	50	100.00
		kmac_test_vectors_shake_256	1.260h	774.765ms	50	50	100.00
		kmac_test_vectors_kmac	5.110s	272.630us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.340s	1.027ms	50	50	100.00
V2	sideload	kmac_sideload	7.040m	33.298ms	50	50	100.00
V2	app	kmac_app	5.553m	66.626ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.189m	5.799ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.212m	15.443ms	50	50	100.00
V2	error	kmac_error	7.160m	27.556ms	50	50	100.00
V2	key_error	kmac_key_error	10.030s	6.605ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.940s	6.331ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.020s	6.221ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.232m	34.551ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.100s	926.530us	50	50	100.00
V2	stress_all	kmac_stress_all	44.995m	133.560ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.850s	62.475us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	33.288us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.890s	1.339ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.890s	1.339ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.980s	63.136us	5	5	100.00
		kmac_csr_rw	1.210s	33.248us	20	20	100.00
		kmac_csr_aliasing	9.380s	493.439us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	125.236us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.980s	63.136us	5	5	100.00
		kmac_csr_rw	1.210s	33.248us	20	20	100.00
		kmac_csr_aliasing	9.380s	493.439us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	125.236us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	53.832us	17	20	85.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	53.832us	17	20	85.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	53.832us	17	20	85.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	53.832us	17	20	85.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	234.902us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.218m	19.028ms	5	5	100.00
		kmac_tl_intg_err	5.030s	903.975us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.030s	903.975us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.100s	926.530us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.209m	8.153ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.040m	33.298ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	53.832us	17	20	85.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.218m	19.028ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.218m	19.028ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.218m	19.028ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.209m	8.153ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.100s	926.530us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.218m	19.028ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.268m	92.006ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.209m	8.153ms	50	50	100.00
V2S		TOTAL			71	75	94.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.820m	121.750ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1231	1250	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.78	95.77	90.51	100.00	66.94	93.67	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 0.kmac_stress_all_with_rand_reset.100750938079901845315422947605610509022114024613902545756346604871703828940303
    Line 663, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131960037838 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 131960037838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.110929723679899062999583887776112696989314806867285135207874498365118037637219
    Line 1150, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 191554019084 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 191554019084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors has 3 failures.

1.kmac_shadow_reg_errors.48484395681767715237054848865968302888938089717577412299553769234450180909076
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  41109736 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  41109736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.20370170510431344513124373460994649298345333928744294339194261101547099952084
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   2718181 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   2718181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

10.kmac_shadow_reg_errors_with_csr_rw.104138797070828563283401929590192019653295906051740835417887280192857305037576
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  29783966 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  29783966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 4 failures.

6.kmac_stress_all.29766051891125692684094493062948509044082006219487668645908411428109774051416
Line 921, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3626326070 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (93 [0x5d] vs 99 [0x63]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3626326070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.kmac_stress_all.46904150486861592417412591834595187473974572291329091359274220373809972788617
Line 591, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/29.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3246530668 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (242 [0xf2] vs 104 [0x68]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3246530668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.29884353608797802688332788105049496147192484032334985775834553142600953192380
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 331344611 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 331344611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 40.kmac_key_error.56571865668496897610110188324674145231732017987054427643203290829145350725503
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_key_error/latest/run.log
```
  UVM_ERROR @  13490590 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @  13490590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```