KMAC/UNMASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.220m 4.215ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.010s 22.748us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.230s 140.875us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 18.470s 1.925ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 9.980s 2.167ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.670s 89.801us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.230s 140.875us 20 20 100.00
kmac_csr_aliasing 9.980s 2.167ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.750s 13.500us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.480s 35.625us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 51.514m 560.546ms 50 50 100.00
V2 burst_write kmac_burst_write 14.132m 36.880ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 35.327m 380.977ms 50 50 100.00
kmac_test_vectors_sha3_256 34.114m 93.038ms 50 50 100.00
kmac_test_vectors_sha3_384 26.972m 290.434ms 50 50 100.00
kmac_test_vectors_sha3_512 21.043m 708.681ms 50 50 100.00
kmac_test_vectors_shake_128 1.677h 4.409s 50 50 100.00
kmac_test_vectors_shake_256 1.426h 2.696s 50 50 100.00
kmac_test_vectors_kmac 5.670s 1.215ms 50 50 100.00
kmac_test_vectors_kmac_xof 5.530s 1.642ms 50 50 100.00
V2 sideload kmac_sideload 7.063m 60.523ms 50 50 100.00
V2 app kmac_app 5.449m 16.920ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 4.502m 29.330ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 5.219m 18.744ms 47 50 94.00
V2 error kmac_error 6.766m 20.451ms 49 50 98.00
V2 key_error kmac_key_error 10.480s 7.175ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 38.550s 1.910ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 37.650s 1.803ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.124m 31.419ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 46.050s 6.580ms 50 50 100.00
V2 stress_all kmac_stress_all 35.111m 119.079ms 50 50 100.00
V2 intr_test kmac_intr_test 0.840s 13.829us 50 50 100.00
V2 alert_test kmac_alert_test 0.900s 27.183us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.360s 143.216us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.360s 143.216us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.010s 22.748us 5 5 100.00
kmac_csr_rw 1.230s 140.875us 20 20 100.00
kmac_csr_aliasing 9.980s 2.167ms 5 5 100.00
kmac_same_csr_outstanding 2.610s 2.289ms 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.010s 22.748us 5 5 100.00
kmac_csr_rw 1.230s 140.875us 20 20 100.00
kmac_csr_aliasing 9.980s 2.167ms 5 5 100.00
kmac_same_csr_outstanding 2.610s 2.289ms 20 20 100.00
V2 TOTAL 1046 1050 99.62
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.460s 228.248us 18 20 90.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.460s 228.248us 18 20 90.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.460s 228.248us 18 20 90.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.460s 228.248us 18 20 90.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.870s 249.548us 19 20 95.00
V2S tl_intg_err kmac_sec_cm 1.157m 8.906ms 5 5 100.00
kmac_tl_intg_err 5.360s 509.360us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.360s 509.360us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 46.050s 6.580ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.220m 4.215ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 7.063m 60.523ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.460s 228.248us 18 20 90.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.157m 8.906ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.157m 8.906ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.157m 8.906ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.220m 4.215ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 46.050s 6.580ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.157m 8.906ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.039m 46.706ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.220m 4.215ms 50 50 100.00
V2S TOTAL 72 75 96.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 36.848m 33.635ms 1 10 10.00
V3 TOTAL 1 10 10.00
TOTAL 1234 1250 98.72

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 23 92.00
V2S 5 5 3 60.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.31 95.89 92.30 100.00 68.60 94.11 98.84 96.43

Failure Buckets

Past Results