KMAC/UNMASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.220m	4.215ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.010s	22.748us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	140.875us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.470s	1.925ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.980s	2.167ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	89.801us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	140.875us	20	20	100.00
		kmac_csr_aliasing	9.980s	2.167ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	13.500us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	35.625us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.514m	560.546ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.132m	36.880ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.327m	380.977ms	50	50	100.00
		kmac_test_vectors_sha3_256	34.114m	93.038ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.972m	290.434ms	50	50	100.00
		kmac_test_vectors_sha3_512	21.043m	708.681ms	50	50	100.00
		kmac_test_vectors_shake_128	1.677h	4.409s	50	50	100.00
		kmac_test_vectors_shake_256	1.426h	2.696s	50	50	100.00
		kmac_test_vectors_kmac	5.670s	1.215ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.530s	1.642ms	50	50	100.00
V2	sideload	kmac_sideload	7.063m	60.523ms	50	50	100.00
V2	app	kmac_app	5.449m	16.920ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.502m	29.330ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.219m	18.744ms	47	50	94.00
V2	error	kmac_error	6.766m	20.451ms	49	50	98.00
V2	key_error	kmac_key_error	10.480s	7.175ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.550s	1.910ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.650s	1.803ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.124m	31.419ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.050s	6.580ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.111m	119.079ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.840s	13.829us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	27.183us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.360s	143.216us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.360s	143.216us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.010s	22.748us	5	5	100.00
		kmac_csr_rw	1.230s	140.875us	20	20	100.00
		kmac_csr_aliasing	9.980s	2.167ms	5	5	100.00
		kmac_same_csr_outstanding	2.610s	2.289ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.010s	22.748us	5	5	100.00
		kmac_csr_rw	1.230s	140.875us	20	20	100.00
		kmac_csr_aliasing	9.980s	2.167ms	5	5	100.00
		kmac_same_csr_outstanding	2.610s	2.289ms	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	228.248us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	228.248us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	228.248us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	228.248us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	249.548us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.157m	8.906ms	5	5	100.00
		kmac_tl_intg_err	5.360s	509.360us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.360s	509.360us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.050s	6.580ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.220m	4.215ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.063m	60.523ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	228.248us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.157m	8.906ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.157m	8.906ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.157m	8.906ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.220m	4.215ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.050s	6.580ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.157m	8.906ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.039m	46.706ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.220m	4.215ms	50	50	100.00
V2S		TOTAL			72	75	96.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.848m	33.635ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1234	1250	98.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.31	95.89	92.30	100.00	68.60	94.11	98.84	96.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.106448555990208768959019245145419557000242805162573463706423269877640167552379
    Line 1836, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 270509199183 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 270509199183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.81368634446983146926557709565742236684006181853583947060985374337726323906905
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234873418 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 234873418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 3 failures:

Test kmac_shadow_reg_errors has 2 failures.

2.kmac_shadow_reg_errors.94136958668744277575334731414079752218416657964855313374593781466065657262814
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   4613310 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   4613310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_shadow_reg_errors.93044858426240600799670055989372074049376510592717764113442019005917357861742
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  12183752 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  12183752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

16.kmac_shadow_reg_errors_with_csr_rw.82097748361936607223481768400341160781689696053293609278216773533989784123308
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  64533488 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  64533488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 2 failures.

4.kmac_entropy_refresh.44207505674394672704522494960767612026308354157832093155293338525744371459114
Line 351, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2005439078 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (177 [0xb1] vs 192 [0xc0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2005439078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_entropy_refresh.74416064102272666602520370077803252701461581713262133777148433232642170325197
Line 441, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 14833837161 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (100 [0x64] vs 174 [0xae]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14833837161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 1 failures.
  - 10.kmac_error.87273864740097683638496819266008768231285843869629811548107124382851525423420
    Line 901, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 46.kmac_entropy_refresh.52126315332243418229881624017421984715894594886882513829015777051296093874286
    Line 1000, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 9.kmac_stress_all_with_rand_reset.72125822620086126967653932347764004927993949241688306843408919656208075377069
    Line 1105, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 192494377419 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 192494377419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```