KMAC/UNMASKED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.090m	3.693ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	59.378us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	211.056us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.400s	1.126ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.630s	635.444us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.880s	154.081us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	211.056us	20	20	100.00
		kmac_csr_aliasing	10.630s	635.444us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	25.466us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	22.188us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	44.509m	413.780ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.128m	141.061ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.367m	1.285s	50	50	100.00
		kmac_test_vectors_sha3_256	33.229m	639.018ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.639m	294.940ms	50	50	100.00
		kmac_test_vectors_sha3_512	21.550m	826.737ms	50	50	100.00
		kmac_test_vectors_shake_128	1.484h	272.444ms	50	50	100.00
		kmac_test_vectors_shake_256	1.328h	1.656s	50	50	100.00
		kmac_test_vectors_kmac	5.120s	497.302us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.640s	975.873us	50	50	100.00
V2	sideload	kmac_sideload	6.590m	14.743ms	50	50	100.00
V2	app	kmac_app	5.362m	59.531ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.123m	171.831ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.623m	19.151ms	48	50	96.00
V2	error	kmac_error	6.557m	18.512ms	49	50	98.00
V2	key_error	kmac_key_error	9.470s	6.072ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.160s	1.520ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.190s	3.369ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.210m	14.934ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.530s	3.870ms	50	50	100.00
V2	stress_all	kmac_stress_all	28.724m	78.935ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.860s	72.392us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	43.421us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.350s	930.993us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.350s	930.993us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	59.378us	5	5	100.00
		kmac_csr_rw	1.260s	211.056us	20	20	100.00
		kmac_csr_aliasing	10.630s	635.444us	5	5	100.00
		kmac_same_csr_outstanding	2.360s	405.393us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	59.378us	5	5	100.00
		kmac_csr_rw	1.260s	211.056us	20	20	100.00
		kmac_csr_aliasing	10.630s	635.444us	5	5	100.00
		kmac_same_csr_outstanding	2.360s	405.393us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	314.641us	18	20	90.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	314.641us	18	20	90.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	314.641us	18	20	90.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	314.641us	18	20	90.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	451.410us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	55.390s	6.073ms	5	5	100.00
		kmac_tl_intg_err	5.210s	537.922us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.210s	537.922us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.530s	3.870ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.090m	3.693ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.590m	14.743ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	314.641us	18	20	90.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.390s	6.073ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.390s	6.073ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.390s	6.073ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.090m	3.693ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.530s	3.870ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.390s	6.073ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.665m	200.000ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.090m	3.693ms	50	50	100.00
V2S		TOTAL			70	75	93.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.155m	88.579ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1232	1250	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	2	40.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.99	95.89	92.27	100.00	66.12	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 0.kmac_stress_all_with_rand_reset.113321317990141735025685716545261488942998897669051792912897696161657448837888
    Line 1850, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 88579048565 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 88579048565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.25577459343161863852279801147354352313608531228736614555857487427336618325011
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7569769144 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7569769144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 4 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.

0.kmac_shadow_reg_errors_with_csr_rw.57375786579273513053310687654709791315185316638318569058241486445914606961955
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  44698571 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  44698571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.kmac_shadow_reg_errors_with_csr_rw.69767623565645299847512431815028158482075840870119091300562134921647040657036
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 270654681 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 270654681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors has 2 failures.

2.kmac_shadow_reg_errors.79915261068037031667484602327363671926967332164515959082382944190869529079393
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  20277916 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  20277916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors.103620777226489321152260650478670901810947744006887491644608237107600379628077
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   9248273 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   9248273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_error has 1 failures.
  - 2.kmac_error.68248815048428155203836233940383703912130882236398231416479291260690213691689
    Line 1188, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_mubi has 1 failures.
  - 6.kmac_mubi.98824289165651671908185545706262351836232120983093149564943992733647075203728
    Line 1023, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 24.kmac_entropy_refresh.21269181681648776143324573950508269094389786907613765644872922712891192800450
    Line 862, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 20.kmac_stress_all.73684472643538986936851113935906634767902999538780939767902716640446456323543
    Line 701, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 5064582231 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (127 [0x7f] vs 23 [0x17]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5064582231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_entropy_refresh has 1 failures.
  - 33.kmac_entropy_refresh.82862063949787242301917028387789695819091687250324521361307072227973022245058
    Line 1085, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 66808800536 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (170 [0xaa] vs 64 [0x40]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 66808800536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```