KMAC/UNMASKED Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.106m	4.008ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	118.472us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	121.643us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.310s	5.206ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.380s	1.059ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.460s	93.096us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	121.643us	20	20	100.00
		kmac_csr_aliasing	10.380s	1.059ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	14.187us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.590s	324.944us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.456m	133.181ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.225m	24.700ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.699m	407.392ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.296m	477.714ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.704m	1.197s	50	50	100.00
		kmac_test_vectors_sha3_512	19.139m	282.502ms	50	50	100.00
		kmac_test_vectors_shake_128	1.825h	5.000s	49	50	98.00
		kmac_test_vectors_shake_256	1.223h	864.687ms	50	50	100.00
		kmac_test_vectors_kmac	5.330s	1.031ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.500s	1.336ms	50	50	100.00
V2	sideload	kmac_sideload	7.020m	14.788ms	50	50	100.00
V2	app	kmac_app	5.043m	18.031ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.715m	50.146ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.506m	13.753ms	48	50	96.00
V2	error	kmac_error	6.763m	29.471ms	50	50	100.00
V2	key_error	kmac_key_error	16.440s	25.522ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	37.780s	1.537ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.180s	1.645ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.518m	111.703ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.045m	4.141ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.703m	230.652ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.840s	16.395us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	17.637us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.940s	154.858us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.940s	154.858us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	118.472us	5	5	100.00
		kmac_csr_rw	1.200s	121.643us	20	20	100.00
		kmac_csr_aliasing	10.380s	1.059ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	470.579us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	118.472us	5	5	100.00
		kmac_csr_rw	1.200s	121.643us	20	20	100.00
		kmac_csr_aliasing	10.380s	1.059ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	470.579us	20	20	100.00
V2		TOTAL			1045	1050	99.52
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.650s	123.344us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.650s	123.344us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.650s	123.344us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.650s	123.344us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.810s	439.792us	17	20	85.00
V2S	tl_intg_err	kmac_sec_cm	1.005m	21.329ms	5	5	100.00
		kmac_tl_intg_err	5.850s	460.182us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.850s	460.182us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.045m	4.141ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.106m	4.008ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.020m	14.788ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.650s	123.344us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.005m	21.329ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.005m	21.329ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.005m	21.329ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.106m	4.008ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.045m	4.141ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.005m	21.329ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.282m	60.434ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.106m	4.008ms	50	50	100.00
V2S		TOTAL			68	75	90.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	18.597m	1.045s	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1228	1250	98.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.60	95.77	90.51	100.00	66.12	93.67	98.84	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.19928414740851036756635216035004594958950730157463414510633045345109398285747
    Line 1622, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1045241464083 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1045241464083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.17154265661476691534821001578559174647500830273840752177837837418212135491530
    Line 1072, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48614309522 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 48614309522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 7 failures:

Test kmac_shadow_reg_errors has 4 failures.

1.kmac_shadow_reg_errors.64223859935429397891587324754717405996231497408565056753545692573265563651333
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @   8843736 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @   8843736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors.89612851699068230467686663957690117563198773548971404481515655973597057549308
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  31454265 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  31454265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

6.kmac_shadow_reg_errors_with_csr_rw.19412935969644338007492189793620045931494023338502544362061394829924484834943
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  72341453 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  72341453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.39525133415426587547098904429179743735736273156418407301196136942139905702307
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  21514764 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  21514764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 2 failures.

0.kmac_entropy_refresh.35755983896536089561593165976683685570712783270601784179704152030696416879248
Line 507, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 2573932680 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (198 [0xc6] vs 7 [0x7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2573932680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.kmac_entropy_refresh.112060432387371633712759007628163538833551095044850731147528161519256453770843
Line 769, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 36802317594 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (167 [0xa7] vs 166 [0xa6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 36802317594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

32.kmac_app.50987042871973338883038145178846070329051986934069368005643105390299323962182
Line 721, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/32.kmac_app/latest/run.log

  UVM_FATAL @ 3013825705 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (50 [0x32] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3013825705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 8.kmac_stress_all_with_rand_reset.67235939894039054670868646672659018004293008339152845176411515723940647152339
    Line 674, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18875065920 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18875065920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.kmac_stress_all_with_rand_reset.105743702751204256498578401601165776943872756913224782874086804099607407382326
    Line 589, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9111705949 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9111705949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 27.kmac_burst_write.39938903220829595150437344828024317241995633461500219654352084483304471915726
    Line 639, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 27.kmac_test_vectors_shake_128.59431200098979394082650593705720766137010194836727196950833785729621101610182
    Line 4937, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```