KMAC/UNMASKED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.140m	4.111ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	52.159us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.090s	29.696us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.060s	4.381ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.180s	1.506ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	192.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.090s	29.696us	20	20	100.00
		kmac_csr_aliasing	9.180s	1.506ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	37.973us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	145.129us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.150m	151.520ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.161m	34.630ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.986m	99.356ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.887m	1.123s	50	50	100.00
		kmac_test_vectors_sha3_384	27.883m	860.510ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.414m	51.493ms	50	50	100.00
		kmac_test_vectors_shake_128	1.761h	2.126s	50	50	100.00
		kmac_test_vectors_shake_256	1.409h	915.278ms	50	50	100.00
		kmac_test_vectors_kmac	5.830s	3.064ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.590s	709.942us	50	50	100.00
V2	sideload	kmac_sideload	7.347m	41.432ms	50	50	100.00
V2	app	kmac_app	6.229m	71.160ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.231m	12.543ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.621m	13.682ms	47	50	94.00
V2	error	kmac_error	7.037m	20.839ms	50	50	100.00
V2	key_error	kmac_key_error	14.080s	18.022ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.350s	6.816ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.850s	1.901ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.299m	18.112ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.148m	6.691ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.141m	54.596ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.820s	12.916us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	18.201us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.650s	637.438us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.650s	637.438us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	52.159us	5	5	100.00
		kmac_csr_rw	1.090s	29.696us	20	20	100.00
		kmac_csr_aliasing	9.180s	1.506ms	5	5	100.00
		kmac_same_csr_outstanding	2.650s	452.747us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	52.159us	5	5	100.00
		kmac_csr_rw	1.090s	29.696us	20	20	100.00
		kmac_csr_aliasing	9.180s	1.506ms	5	5	100.00
		kmac_same_csr_outstanding	2.650s	452.747us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	506.829us	16	20	80.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	506.829us	16	20	80.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	506.829us	16	20	80.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	506.829us	16	20	80.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.070s	519.951us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.316m	21.545ms	5	5	100.00
		kmac_tl_intg_err	5.170s	508.825us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.170s	508.825us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.148m	6.691ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.140m	4.111ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.347m	41.432ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	506.829us	16	20	80.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.316m	21.545ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.316m	21.545ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.316m	21.545ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.140m	4.111ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.148m	6.691ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.316m	21.545ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.073m	46.046ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.140m	4.111ms	50	50	100.00
V2S		TOTAL			66	75	88.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	19.398m	171.994ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1224	1250	97.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	3	60.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.45	95.89	92.30	100.00	69.42	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 1.kmac_stress_all_with_rand_reset.90055967462777125824639769341350777077056909170487068612288509532656654284048
    Line 824, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 59122667132 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 59122667132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.6071156974650524302672401150938872862764026538194572535412695025654893475005
    Line 593, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30990904150 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30990904150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: * Check_csr_read_clear_staged_val task: check update_err status has 8 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

2.kmac_shadow_reg_errors_with_csr_rw.115142701571341027024104098000065885797563519433793365878642265319702754271752
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 130792908 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @ 130792908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.30389972086381311628539455412434664794581892690745843501332990549148578660419
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  55242921 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  55242921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_shadow_reg_errors has 4 failures.

7.kmac_shadow_reg_errors.93403850577713612878043566081975943510304262764572035786260246239410782401368
Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  17569000 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  17569000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors.113041709854046977243834282939389336921299799119089659860950564261598667260608
Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_ERROR @  26741001 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: kmac_reg_block.status.alert_recov_ctrl_update_err reset value: 0x0  Check_csr_read_clear_staged_val task: check update_err status
  UVM_INFO @  26741001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_burst_write has 3 failures.
  - 24.kmac_burst_write.69772883253138055826941470291006431652402325124268342647415507618630672764036
    Line 1047, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.kmac_burst_write.66385636932588932390886848976558782229961186262220017198255993496084205544735
    Line 872, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_entropy_refresh has 1 failures.
  - 37.kmac_entropy_refresh.12744133590553687551986869535935274126578406051575669286337043210053827572733
    Line 822, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/37.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 2 failures.

13.kmac_entropy_refresh.14679525205930473302704787727931028013536279526420365650536143605953328324935
Line 335, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 718699902 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 41 [0x29]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 718699902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_entropy_refresh.63076389942297765000422032905772361038264632960271916167444048359984787849915
Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 749636775 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (37 [0x25] vs 141 [0x8d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 749636775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

46.kmac_app.28340053553412911665588943556181681842750960904565637634461808784688938614012
Line 787, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_app/latest/run.log

  UVM_FATAL @ 146201900742 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (23 [0x17] vs 77 [0x4d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 146201900742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 4.kmac_shadow_reg_errors_with_csr_rw.13178303513118072399457035015883353522609483527381483591663685484562664670069
    Line 265, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  65519477 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (76899459 [0x4956483] vs 0 [0x0]) Regname: kmac_reg_block.prefix_2.prefix_0 reset value: 0x0
  UVM_INFO @  65519477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 49.kmac_key_error.115360148772993565286072456213819765615501667408897461848869301359098998035369
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 3766029911 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 3766029911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```