KMAC/UNMASKED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.395m	53.471ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.110s	103.388us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	130.665us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.930s	6.023ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.470s	963.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	314.037us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	130.665us	20	20	100.00
		kmac_csr_aliasing	9.470s	963.775us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	19.307us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.390s	20.057us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.802m	517.015ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.908m	167.587ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.597m	510.639ms	50	50	100.00
		kmac_test_vectors_sha3_256	36.951m	1.307s	50	50	100.00
		kmac_test_vectors_sha3_384	25.549m	281.540ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.196m	302.121ms	50	50	100.00
		kmac_test_vectors_shake_128	1.613h	1.985s	50	50	100.00
		kmac_test_vectors_shake_256	1.385h	2.738s	50	50	100.00
		kmac_test_vectors_kmac	5.110s	1.343ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.290s	1.021ms	50	50	100.00
V2	sideload	kmac_sideload	6.774m	28.559ms	50	50	100.00
V2	app	kmac_app	6.693m	59.969ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.985m	14.308ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.831m	32.024ms	50	50	100.00
V2	error	kmac_error	6.719m	48.634ms	50	50	100.00
V2	key_error	kmac_key_error	9.860s	1.733ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.570s	4.608ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.790s	3.968ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.088m	14.573ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.125m	1.063ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.669m	30.004ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.900s	17.680us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	24.138us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.350s	112.388us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.350s	112.388us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.110s	103.388us	5	5	100.00
		kmac_csr_rw	1.210s	130.665us	20	20	100.00
		kmac_csr_aliasing	9.470s	963.775us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	115.503us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.110s	103.388us	5	5	100.00
		kmac_csr_rw	1.210s	130.665us	20	20	100.00
		kmac_csr_aliasing	9.470s	963.775us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	115.503us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	60.822us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	60.822us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	60.822us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	60.822us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.930s	516.386us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	55.930s	9.207ms	5	5	100.00
		kmac_tl_intg_err	4.920s	709.348us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.920s	709.348us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.125m	1.063ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.395m	53.471ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.774m	28.559ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	60.822us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.930s	9.207ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.930s	9.207ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.930s	9.207ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.395m	53.471ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.125m	1.063ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.930s	9.207ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.200m	3.789ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.395m	53.471ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	35.038m	224.753ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1238	1250	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.08	95.77	90.55	100.00	69.42	93.67	98.84	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test kmac_stress_all_with_rand_reset has 10 failures.

    • 0.kmac_stress_all_with_rand_reset.74279681081766093642906285753031024256614595055189901841071926402773725825235
      Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2972331956 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2972331956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.77646295206501656230393808308728814369762237973020871852864258968041757360716
      Line 1262, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 200896427119 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 200896427119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_burst_write has 1 failures.

    • 5.kmac_burst_write.38818800807252793881779099513348513286899901001422001454337235532536085339075
      Line 956, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 35.kmac_stress_all.114330750849130551582801553143288292829378247534162999626914855523469252160334
      Line 2157, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all/latest/run.log

        UVM_FATAL @ 44908719515 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (180 [0xb4] vs 162 [0xa2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 44908719515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.12_09.08.20
• 2024.07.11_10.34.16
• 2024.07.10_10.41.32
• 2024.07.08_10.11.35
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