KMAC/UNMASKED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.149m	8.554ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	291.058us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	49.559us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.690s	371.470us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.350s	144.624us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.500s	86.520us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	49.559us	20	20	100.00
		kmac_csr_aliasing	8.350s	144.624us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	17.033us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	138.880us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.096m	365.777ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.387m	108.043ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.747m	511.289ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.290m	500.263ms	50	50	100.00
		kmac_test_vectors_sha3_384	26.257m	849.875ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.255m	402.671ms	50	50	100.00
		kmac_test_vectors_shake_128	1.710h	3.675s	50	50	100.00
		kmac_test_vectors_shake_256	1.385h	4.370s	50	50	100.00
		kmac_test_vectors_kmac	5.380s	989.405us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.290s	1.030ms	50	50	100.00
V2	sideload	kmac_sideload	6.566m	74.468ms	50	50	100.00
V2	app	kmac_app	5.519m	67.756ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.758m	15.493ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.409m	74.907ms	49	50	98.00
V2	error	kmac_error	6.440m	74.085ms	50	50	100.00
V2	key_error	kmac_key_error	9.340s	13.528ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.260s	1.998ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.100s	2.453ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.920s	24.632ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.940s	887.611us	50	50	100.00
V2	stress_all	kmac_stress_all	35.014m	25.470ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	25.455us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	22.653us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.310s	510.070us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.310s	510.070us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	291.058us	5	5	100.00
		kmac_csr_rw	1.240s	49.559us	20	20	100.00
		kmac_csr_aliasing	8.350s	144.624us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	127.255us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	291.058us	5	5	100.00
		kmac_csr_rw	1.240s	49.559us	20	20	100.00
		kmac_csr_aliasing	8.350s	144.624us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	127.255us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	179.973us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	179.973us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	179.973us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	179.973us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.820s	1.366ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	57.160s	5.857ms	5	5	100.00
		kmac_tl_intg_err	5.050s	205.989us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.050s	205.989us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.940s	887.611us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.149m	8.554ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.566m	74.468ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	179.973us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	57.160s	5.857ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	57.160s	5.857ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	57.160s	5.857ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.149m	8.554ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.940s	887.611us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	57.160s	5.857ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.504m	80.989ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.149m	8.554ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.939m	71.150ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1238	1250	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.23	95.89	92.27	100.00	67.77	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.13167022243442860785294341156170549202702851126404649627325382396760255815643
    Line 1521, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64326293616 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 64326293616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.92597437507985530433456021623536226380683256379698090427092106946642457636812
    Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5490868378 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5490868378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 1 failures.

3.kmac_entropy_refresh.37237900179983571287065075496022115178884719991095099640808592870420291854684
Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 652885414 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (17 [0x11] vs 255 [0xff]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 652885414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

12.kmac_app.93728376529310754702196888589553579469493572982524491934713611548807941898215
Line 339, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_app/latest/run.log

  UVM_FATAL @ 7100448461 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 194 [0xc2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7100448461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_app.108993568588018562773181521783448108802315739637247212552101453653756166506117
Line 307, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_app/latest/run.log

  UVM_FATAL @ 2473249376 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (36 [0x24] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2473249376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_mubi has 1 failures.
  - 4.kmac_mubi.56859777574385999858993305070574161379007909596828183064241689564105190180249
    Line 759, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 15.kmac_burst_write.54597828693788465178057081125528831852276622053310910653050005225933387400792
    Line 807, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 4.kmac_stress_all_with_rand_reset.67460195492005517589636851715562777473789554526649193187572737987149446938538
    Line 1425, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46384505900 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 46384505900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.14838888151172128530683454423480760620813360846549167610065323731162521812878
    Line 2072, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21908380552 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 21908380552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```