KMAC/UNMASKED Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.126m	2.921ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.140s	83.410us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	98.410us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.050s	1.489ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.120s	557.385us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.540s	92.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	98.410us	20	20	100.00
		kmac_csr_aliasing	8.120s	557.385us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	21.832us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	236.287us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.647m	500.529ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.429m	34.009ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.882m	1.626s	50	50	100.00
		kmac_test_vectors_sha3_256	34.122m	510.147ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.651m	68.805ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.905m	474.123ms	50	50	100.00
		kmac_test_vectors_shake_128	1.469h	921.736ms	50	50	100.00
		kmac_test_vectors_shake_256	1.299h	2.334s	50	50	100.00
		kmac_test_vectors_kmac	5.720s	1.270ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.980s	3.443ms	50	50	100.00
V2	sideload	kmac_sideload	7.380m	21.043ms	50	50	100.00
V2	app	kmac_app	5.973m	17.398ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.881m	13.145ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.469m	5.279ms	49	50	98.00
V2	error	kmac_error	7.179m	27.645ms	49	50	98.00
V2	key_error	kmac_key_error	12.190s	12.282ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.930s	3.527ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.990s	8.304ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.079m	11.425ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.260s	574.726us	50	50	100.00
V2	stress_all	kmac_stress_all	30.541m	23.430ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.820s	48.652us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	63.939us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.530s	468.813us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.530s	468.813us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.140s	83.410us	5	5	100.00
		kmac_csr_rw	1.170s	98.410us	20	20	100.00
		kmac_csr_aliasing	8.120s	557.385us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	336.741us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.140s	83.410us	5	5	100.00
		kmac_csr_rw	1.170s	98.410us	20	20	100.00
		kmac_csr_aliasing	8.120s	557.385us	5	5	100.00
		kmac_same_csr_outstanding	2.650s	336.741us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.340s	113.531us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.340s	113.531us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.340s	113.531us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.340s	113.531us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.430s	1.702ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.265m	5.662ms	5	5	100.00
		kmac_tl_intg_err	5.010s	548.875us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.010s	548.875us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.260s	574.726us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.126m	2.921ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.380m	21.043ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.340s	113.531us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.265m	5.662ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.265m	5.662ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.265m	5.662ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.126m	2.921ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.260s	574.726us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.265m	5.662ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.866m	4.277ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.126m	2.921ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.503m	115.646ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1237	1250	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.47	95.89	92.30	100.00	69.42	94.11	98.84	96.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 0.kmac_stress_all_with_rand_reset.62793035192029524562098477369153598364305746808356994113472016971248594543332
      Line 2406, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 67744820549 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 67744820549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.110352773046277596177164858128097076112056606186962505829004536516919140129233
      Line 335, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21322067392 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 21322067392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test kmac_burst_write has 2 failures.

    • 17.kmac_burst_write.17994169117475150727058366263291206477011426636834468971629697256108534991823
      Line 1400, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.kmac_burst_write.28077083402118049379342051297076362547330574649568277584623955678782932364481
      Line 1076, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_error has 1 failures.

    • 45.kmac_error.7283814475531780076099646975323238034361388194367757640205138468802563471160
      Line 883, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 33.kmac_entropy_refresh.28941062217620930018155642728408182132380534778775326066306160614883561551404
      Line 617, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 17505316372 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 17505316372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_stress_all has 1 failures.

    • 41.kmac_stress_all.57688069257785102148486837364735814194958341128524958034853538178746064953418
      Line 697, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest/run.log

        UVM_FATAL @ 1646752727 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 195 [0xc3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 1646752727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 21.kmac_key_error.1119860613028225603489129947613992318692192743655987847295940543695407493455
      Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_key_error/latest/run.log

        UVM_ERROR @ 425154062 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 425154062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.07.19_08.49.33
• 2024.07.18_09.21.01
• 2024.07.17_09.31.07
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