KMAC/UNMASKED Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.042m	25.980ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	46.100us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	222.928us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.700s	999.305us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.250s	383.661us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.900s	308.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	222.928us	20	20	100.00
		kmac_csr_aliasing	9.250s	383.661us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	10.995us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.450s	68.191us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.572m	121.168ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.152m	66.829ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.822m	576.929ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.621m	615.760ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.922m	868.139ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.214m	470.756ms	50	50	100.00
		kmac_test_vectors_shake_128	1.600h	513.659ms	50	50	100.00
		kmac_test_vectors_shake_256	1.456h	3.089s	50	50	100.00
		kmac_test_vectors_kmac	5.270s	266.240us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.620s	2.889ms	50	50	100.00
V2	sideload	kmac_sideload	7.169m	67.800ms	50	50	100.00
V2	app	kmac_app	5.583m	38.341ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.062m	40.204ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.291m	171.830ms	48	50	96.00
V2	error	kmac_error	7.322m	73.206ms	50	50	100.00
V2	key_error	kmac_key_error	18.720s	32.271ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.500s	6.052ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.130s	2.175ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.315m	31.468ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.560s	2.003ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.601m	30.531ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.860s	13.296us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	35.372us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.440s	387.498us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.440s	387.498us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	46.100us	5	5	100.00
		kmac_csr_rw	1.260s	222.928us	20	20	100.00
		kmac_csr_aliasing	9.250s	383.661us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	256.950us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	46.100us	5	5	100.00
		kmac_csr_rw	1.260s	222.928us	20	20	100.00
		kmac_csr_aliasing	9.250s	383.661us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	256.950us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	36.150us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	36.150us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	36.150us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	36.150us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	222.282us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.375m	11.403ms	5	5	100.00
		kmac_tl_intg_err	5.400s	2.995ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.400s	2.995ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.560s	2.003ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.042m	25.980ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.169m	67.800ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	36.150us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.375m	11.403ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.375m	11.403ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.375m	11.403ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.042m	25.980ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.560s	2.003ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.375m	11.403ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.141m	30.831ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.042m	25.980ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	23.008m	66.626ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1236	1250	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.47	95.89	92.30	100.00	69.42	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.27690391550046434138313316371536025502566826535935762081754158613735572640867
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3863522956 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3863522956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.100708520288258239263057173641787620007610058023745508872819306846514385225787
    Line 1411, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 66625500225 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 66625500225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

1.kmac_app_with_partial_data.26650952952512648780350416067712432128027892652524267598911496603555394502442
Line 397, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 7184017112 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 89 [0x59]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7184017112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

17.kmac_app.62621533020289351321547052541250627747601490522746227716752277275940013917348
Line 681, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_app/latest/run.log

  UVM_FATAL @ 8081931473 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (56 [0x38] vs 222 [0xde]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8081931473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

26.kmac_entropy_refresh.96223910537670328111474604455408203760577266281631996364980932835550471493559
Line 531, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 34340207110 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (184 [0xb8] vs 139 [0x8b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 34340207110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_entropy_refresh.48042409471628241187863042459559186906825760863845782792252734023349883346108
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8689973607 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (196 [0xc4] vs 42 [0x2a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8689973607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 2 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 2 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.69284728245179900329795722724240392589653275880971811437168304220950561036475
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   7887433 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (524022264 [0x1f3bf1f8] vs 0 [0x0]) Regname: kmac_reg_block.prefix_7 reset value: 0x0
  UVM_INFO @   7887433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_shadow_reg_errors_with_csr_rw.66039903414824017049547490775692382886376638749924312038450781724985474860346
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  37097168 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3266196833 [0xc2ae3561] vs 0 [0x0]) Regname: kmac_reg_block.prefix_7 reset value: 0x0
  UVM_INFO @  37097168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.108526236726114076413791952128183869735543707088045403836229075451119114755409
    Line 856, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12176422787 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 12176422787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```