KMAC/UNMASKED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.134m 4.225ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.120s 31.322us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.180s 30.352us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 20.570s 3.195ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.080s 2.006ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.700s 351.259us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.180s 30.352us 20 20 100.00
kmac_csr_aliasing 10.080s 2.006ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.760s 15.018us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.440s 84.358us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 57.402m 81.966ms 37 50 74.00
V2 burst_write kmac_burst_write 18.274m 80.256ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 59.447m 100.975ms 48 50 96.00
kmac_test_vectors_sha3_256 56.642m 386.672ms 50 50 100.00
kmac_test_vectors_sha3_384 38.722m 455.460ms 50 50 100.00
kmac_test_vectors_sha3_512 27.204m 53.764ms 50 50 100.00
kmac_test_vectors_shake_128 1.648h 207.719ms 23 50 46.00
kmac_test_vectors_shake_256 1.316h 45.297ms 20 50 40.00
kmac_test_vectors_kmac 6.250s 1.037ms 50 50 100.00
kmac_test_vectors_kmac_xof 5.730s 909.349us 50 50 100.00
V2 sideload kmac_sideload 7.994m 58.420ms 50 50 100.00
V2 app kmac_app 6.514m 72.959ms 48 50 96.00
V2 app_with_partial_data kmac_app_with_partial_data 6.212m 19.373ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 6.375m 90.328ms 48 50 96.00
V2 error kmac_error 7.169m 18.839ms 49 50 98.00
V2 key_error kmac_key_error 9.920s 1.954ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 40.670s 7.904ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 36.330s 1.472ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.056m 27.919ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 48.960s 1.532ms 50 50 100.00
V2 stress_all kmac_stress_all 31.071m 81.641ms 48 50 96.00
V2 intr_test kmac_intr_test 0.830s 110.770us 50 50 100.00
V2 alert_test kmac_alert_test 0.910s 30.415us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.590s 601.705us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.590s 601.705us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.120s 31.322us 5 5 100.00
kmac_csr_rw 1.180s 30.352us 20 20 100.00
kmac_csr_aliasing 10.080s 2.006ms 5 5 100.00
kmac_same_csr_outstanding 2.630s 332.082us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.120s 31.322us 5 5 100.00
kmac_csr_rw 1.180s 30.352us 20 20 100.00
kmac_csr_aliasing 10.080s 2.006ms 5 5 100.00
kmac_same_csr_outstanding 2.630s 332.082us 20 20 100.00
V2 TOTAL 971 1050 92.48
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.390s 47.377us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.390s 47.377us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.390s 47.377us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.390s 47.377us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.210s 909.645us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.471m 19.542ms 5 5 100.00
kmac_tl_intg_err 5.350s 847.120us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.350s 847.120us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 48.960s 1.532ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.134m 4.225ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 7.994m 58.420ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.390s 47.377us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.471m 19.542ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.471m 19.542ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.471m 19.542ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.134m 4.225ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 48.960s 1.532ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.471m 19.542ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 6.483m 67.901ms 9 10 90.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.134m 4.225ms 50 50 100.00
V2S TOTAL 74 75 98.67
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 26.065m 308.698ms 2 10 20.00
V3 TOTAL 2 10 20.00
TOTAL 1162 1250 92.96

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 17 68.00
V2S 5 5 4 80.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.33 95.89 92.30 100.00 68.60 94.11 98.84 96.58

Failure Buckets

Past Results