KMAC/UNMASKED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.134m	4.225ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	31.322us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	30.352us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.570s	3.195ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.080s	2.006ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.700s	351.259us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	30.352us	20	20	100.00
		kmac_csr_aliasing	10.080s	2.006ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	15.018us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	84.358us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.402m	81.966ms	37	50	74.00
V2	burst_write	kmac_burst_write	18.274m	80.256ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.447m	100.975ms	48	50	96.00
		kmac_test_vectors_sha3_256	56.642m	386.672ms	50	50	100.00
		kmac_test_vectors_sha3_384	38.722m	455.460ms	50	50	100.00
		kmac_test_vectors_sha3_512	27.204m	53.764ms	50	50	100.00
		kmac_test_vectors_shake_128	1.648h	207.719ms	23	50	46.00
		kmac_test_vectors_shake_256	1.316h	45.297ms	20	50	40.00
		kmac_test_vectors_kmac	6.250s	1.037ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.730s	909.349us	50	50	100.00
V2	sideload	kmac_sideload	7.994m	58.420ms	50	50	100.00
V2	app	kmac_app	6.514m	72.959ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.212m	19.373ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.375m	90.328ms	48	50	96.00
V2	error	kmac_error	7.169m	18.839ms	49	50	98.00
V2	key_error	kmac_key_error	9.920s	1.954ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.670s	7.904ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.330s	1.472ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.056m	27.919ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.960s	1.532ms	50	50	100.00
V2	stress_all	kmac_stress_all	31.071m	81.641ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.830s	110.770us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	30.415us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.590s	601.705us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.590s	601.705us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	31.322us	5	5	100.00
		kmac_csr_rw	1.180s	30.352us	20	20	100.00
		kmac_csr_aliasing	10.080s	2.006ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	332.082us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	31.322us	5	5	100.00
		kmac_csr_rw	1.180s	30.352us	20	20	100.00
		kmac_csr_aliasing	10.080s	2.006ms	5	5	100.00
		kmac_same_csr_outstanding	2.630s	332.082us	20	20	100.00
V2		TOTAL			971	1050	92.48
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.390s	47.377us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.390s	47.377us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.390s	47.377us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.390s	47.377us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	909.645us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.471m	19.542ms	5	5	100.00
		kmac_tl_intg_err	5.350s	847.120us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.350s	847.120us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.960s	1.532ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.134m	4.225ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.994m	58.420ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.390s	47.377us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.471m	19.542ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.471m	19.542ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.471m	19.542ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.134m	4.225ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.960s	1.532ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.471m	19.542ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.483m	67.901ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.134m	4.225ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	26.065m	308.698ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1162	1250	92.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.89	92.30	100.00	68.60	94.11	98.84	96.58

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 72 failures:
- Test kmac_test_vectors_shake_128 has 27 failures.
  - 0.kmac_test_vectors_shake_128.25366141744051625972827029652174253494676637046235581397007464432901002529162
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:36adc728-2eb6-4f7f-9fdd-6f2c882d87d5
```
  - 3.kmac_test_vectors_shake_128.2149222297538896774849733411630112214002176648674923705155890040875514519825
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:456175ad-5976-4043-8f4c-af67bba07d9a
```
  - ... and 25 more failures.
- Test kmac_test_vectors_shake_256 has 30 failures.
  - 0.kmac_test_vectors_shake_256.631904585825476090766172340001436958021417688171287258158118817973566131132
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:f300b885-909e-4dbc-9f8e-73c870404784
```
  - 2.kmac_test_vectors_shake_256.101773160743727691842364393278419290158346797360566818622696565628649664976217
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:6463bcb6-f9bd-43a1-a1ac-baa72a5275e5
```
  - ... and 28 more failures.
- Test kmac_long_msg_and_output has 13 failures.
  - 2.kmac_long_msg_and_output.10852321794559740359493370628447799188638803841825559206145574017991915608000
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:1799e6bb-4969-46fa-b19b-8a2c419c0d3d
```
  - 3.kmac_long_msg_and_output.81528046104640270658298064878707895107816733359825225339196976133070737824720
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:eb0d3581-6fcd-4c41-9e5e-cfafc9d06eaf
```
  - ... and 11 more failures.
- Test kmac_test_vectors_sha3_224 has 2 failures.
  - 17.kmac_test_vectors_sha3_224.112784500650652575660898245657107592124728256573385145511651230973157482344959
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:f340f1bd-9642-48f6-9c9b-887f68751a4c
```
  - 46.kmac_test_vectors_sha3_224.58187744793395008993581872919465647288621823447053680679307109351991644801820
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/46.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:e73c1202-1414-49b1-ba4b-f67b9790164b
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.70385952698536129112860752282658239641438786071715459857994621064852007132662
    Line 596, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37483046292 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 37483046292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.33221589565281463152789367495132880196830417117972345472972177239116044227171
    Line 1083, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 90061615444 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 90061615444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_app has 2 failures.

1.kmac_app.33075818094734812219846805820544213170725150510680371556825266869202761731887
Line 1029, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 10863104091 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (18 [0x12] vs 102 [0x66]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10863104091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_app.10295361406698607219782601949098352635202680164329195389929657444937314917476
Line 1083, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_app/latest/run.log

  UVM_FATAL @ 16833003521 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (206 [0xce] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16833003521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

2.kmac_mubi.72621744623313731227121734766099876239083821896218136974576771345118964513981
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 270095309 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (91 [0x5b] vs 144 [0x90]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 270095309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

34.kmac_entropy_refresh.58451332288270899332523547416736131712692963264478934193369520936343523752370
Line 601, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 16379160996 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (167 [0xa7] vs 107 [0x6b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16379160996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.kmac_entropy_refresh.42123689258234627680893219902342394970780012159900660447494540389345916896398
Line 759, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4099923186 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (34 [0x22] vs 236 [0xec]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4099923186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

38.kmac_stress_all.104998634169030240576479979159093860862819819048285548355495921476758507047119
Line 329, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_FATAL @ 17111840783 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (177 [0xb1] vs 5 [0x5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17111840783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.kmac_stress_all.24668163799598518380878869318230810515392778950591987612573027035448547350360
Line 779, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_stress_all/latest/run.log

  UVM_FATAL @ 13386508785 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (39 [0x27] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13386508785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 16.kmac_error.1614889758762009083800394555074797091587869984815427616301062047959424440434
    Line 995, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```