KMAC/UNMASKED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.159m	4.406ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	34.319us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.310s	223.701us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.220s	1.172ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.500s	1.887ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	39.927us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.310s	223.701us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.887ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.750s	31.075us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.610s	66.125us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.074m	107.324ms	38	50	76.00
V2	burst_write	kmac_burst_write	17.087m	31.415ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.334m	398.851ms	44	50	88.00
		kmac_test_vectors_sha3_256	58.708m	95.842ms	50	50	100.00
		kmac_test_vectors_sha3_384	43.040m	294.431ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.684m	48.149ms	50	50	100.00
		kmac_test_vectors_shake_128	1.682h	122.230ms	22	50	44.00
		kmac_test_vectors_shake_256	1.392h	44.042ms	20	50	40.00
		kmac_test_vectors_kmac	6.630s	2.260ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.900s	1.924ms	50	50	100.00
V2	sideload	kmac_sideload	7.377m	79.238ms	50	50	100.00
V2	app	kmac_app	6.316m	16.551ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.210m	33.988ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.029m	34.480ms	49	50	98.00
V2	error	kmac_error	8.117m	162.874ms	50	50	100.00
V2	key_error	kmac_key_error	10.890s	10.431ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.080s	4.083ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.740s	4.091ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.097m	12.439ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.700s	3.057ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.949m	442.290ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.870s	23.316us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	20.756us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.020s	2.127ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.020s	2.127ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	34.319us	5	5	100.00
		kmac_csr_rw	1.310s	223.701us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.887ms	5	5	100.00
		kmac_same_csr_outstanding	2.820s	465.464us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	34.319us	5	5	100.00
		kmac_csr_rw	1.310s	223.701us	20	20	100.00
		kmac_csr_aliasing	9.500s	1.887ms	5	5	100.00
		kmac_same_csr_outstanding	2.820s	465.464us	20	20	100.00
V2		TOTAL			970	1050	92.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	186.335us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	186.335us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	186.335us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	186.335us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.730s	135.522us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.067m	18.147ms	5	5	100.00
		kmac_tl_intg_err	5.110s	659.926us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	659.926us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.700s	3.057ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.159m	4.406ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.377m	79.238ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	186.335us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.067m	18.147ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.067m	18.147ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.067m	18.147ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.159m	4.406ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.700s	3.057ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.067m	18.147ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.444m	10.853ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.159m	4.406ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.586m	209.564ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1164	1250	93.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.28	95.89	92.27	100.00	68.60	94.11	98.84	96.29

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 76 failures:
- Test kmac_test_vectors_shake_256 has 30 failures.
  - 1.kmac_test_vectors_shake_256.23743843956012082211640083744962918888188332094096528295063535169591100318738
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:f2a6b6b5-785a-4d15-ade1-3f40a44f2095
```
  - 2.kmac_test_vectors_shake_256.9392692548316920946055615910924904920794289861559768931394761116535793682756
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:154724b7-30e0-4f64-ab01-ee28497b6381
```
  - ... and 28 more failures.
- Test kmac_test_vectors_sha3_224 has 6 failures.
  - 2.kmac_test_vectors_sha3_224.66403764361661949643555211773020816113481105068369990270931405903096453046653
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:5de3a466-b951-4f8a-86b1-bc19c1b3a573
```
  - 12.kmac_test_vectors_sha3_224.95871400275215804614351089258670779775406989418312486389560144558775960700015
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:9533e3d7-3d21-44af-be2e-0bccea50a694
```
  - ... and 4 more failures.
- Test kmac_long_msg_and_output has 12 failures.
  - 3.kmac_long_msg_and_output.55067302200328569533371900120255012796618111302235767126713157312447634809723
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:2cf50420-1948-4d55-966c-f85a2b688ec7
```
  - 4.kmac_long_msg_and_output.23126382528221762971429868703585159613454944843526419169245223847617521446064
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:2df09793-ad23-495c-876b-d6a938f3063f
```
  - ... and 10 more failures.
- Test kmac_test_vectors_shake_128 has 28 failures.
  - 3.kmac_test_vectors_shake_128.64904502877538397098833335504036904761269796112837852162772186283430027549789
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:44e2c94b-2187-405d-86d9-36321e727868
```
  - 4.kmac_test_vectors_shake_128.89477690362871944226422716425816475077826578472223007745138287455929916836114
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:b4f6aa65-5357-4cca-9b60-5373af8fc09c
```
  - ... and 26 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.42803440029114903605653502538310129591750033766682642420114376993486948240721
    Line 671, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11612886409 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11612886409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.89451136310473743633686145960535153389227723461073701618827751857905067092427
    Line 1552, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52847288755 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 52847288755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 4 failures:

Test kmac_entropy_refresh has 1 failures.

19.kmac_entropy_refresh.39704734283245712714635907810657029438989184895332851213010728248073418815150
Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 16633520771 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (230 [0xe6] vs 16 [0x10]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16633520771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

20.kmac_app.29685894166813519298939121798826527553613059251721052072612510133845273486243
Line 817, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_app/latest/run.log

  UVM_FATAL @ 21718000059 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 202 [0xca]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21718000059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_app.21150437959969806910707324734615048031706150272186729264585501371649596678907
Line 305, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_app/latest/run.log

  UVM_FATAL @ 1708317050 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (83 [0x53] vs 97 [0x61]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1708317050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.87444126493895892886216731056865462108885321245786239305510941218521589047706
    Line 836, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8731968439 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 8731968439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```