KMAC/UNMASKED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.116m	23.134ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	492.697us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.170s	78.306us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.320s	5.765ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.030s	280.340us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	75.069us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.170s	78.306us	20	20	100.00
		kmac_csr_aliasing	8.030s	280.340us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	56.899us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	63.689us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.373m	1.328s	39	50	78.00
V2	burst_write	kmac_burst_write	19.428m	32.653ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.684m	163.266ms	48	50	96.00
		kmac_test_vectors_sha3_256	56.361m	383.103ms	50	50	100.00
		kmac_test_vectors_sha3_384	44.267m	479.123ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.345m	49.824ms	50	50	100.00
		kmac_test_vectors_shake_128	1.667h	89.531ms	20	50	40.00
		kmac_test_vectors_shake_256	1.331h	44.828ms	20	50	40.00
		kmac_test_vectors_kmac	6.200s	966.033us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.870s	258.156us	50	50	100.00
V2	sideload	kmac_sideload	8.261m	60.343ms	50	50	100.00
V2	app	kmac_app	5.997m	29.623ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.419m	8.688ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.651m	102.998ms	48	50	96.00
V2	error	kmac_error	6.949m	17.484ms	50	50	100.00
V2	key_error	kmac_key_error	13.400s	13.696ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.500s	2.041ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.500s	6.046ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.190m	8.628ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.410s	3.304ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.962m	882.304ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.860s	100.592us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	195.809us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.570s	403.029us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.570s	403.029us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	492.697us	5	5	100.00
		kmac_csr_rw	1.170s	78.306us	20	20	100.00
		kmac_csr_aliasing	8.030s	280.340us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	234.666us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	492.697us	5	5	100.00
		kmac_csr_rw	1.170s	78.306us	20	20	100.00
		kmac_csr_aliasing	8.030s	280.340us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	234.666us	20	20	100.00
V2		TOTAL			971	1050	92.48
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.690s	137.390us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.690s	137.390us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.690s	137.390us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.690s	137.390us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.060s	140.520us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.335m	10.813ms	5	5	100.00
		kmac_tl_intg_err	5.250s	1.076ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.250s	1.076ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.410s	3.304ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.116m	23.134ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.261m	60.343ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.690s	137.390us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.335m	10.813ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.335m	10.813ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.335m	10.813ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.116m	23.134ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.410s	3.304ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.335m	10.813ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.770m	18.402ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.116m	23.134ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.370m	175.307ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1162	1250	92.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.33	95.89	92.30	100.00	68.60	94.11	98.84	96.58

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 73 failures:
- Test kmac_long_msg_and_output has 11 failures.
  - 1.kmac_long_msg_and_output.66307660921551219563079166529995949523014085732958609920529383934164469443651
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:bb837f44-6a55-487f-a7f7-d279743dbc04
```
  - 9.kmac_long_msg_and_output.31759065191667882077510481971677791591199116432501154046981579192744758940976
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:a1cc9872-1f64-47e5-ba04-252b6a7c68a1
```
  - ... and 9 more failures.
- Test kmac_test_vectors_shake_128 has 30 failures.
  - 1.kmac_test_vectors_shake_128.111640236113065428997480481565365381042416625364607084643466165365164218847361
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:7700c66d-11f6-4d38-8b7c-3b78ba75f497
```
  - 3.kmac_test_vectors_shake_128.108932247338139779835045052995068936908691512603024441905216447077020363610366
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:7c2c6b6d-c880-4d72-8ad0-26e140962537
```
  - ... and 28 more failures.
- Test kmac_test_vectors_shake_256 has 30 failures.
  - 1.kmac_test_vectors_shake_256.109078016632489123476240964630052824196069000045305510677086799838870021007976
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:790c352f-198a-4827-ba92-6205bbaabe05
```
  - 3.kmac_test_vectors_shake_256.108240766078241684856914324090436935167507289717598883173668719615888543318611
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:300c37ef-8adc-4053-8a8e-8312a3962172
```
  - ... and 28 more failures.
- Test kmac_test_vectors_sha3_224 has 2 failures.
  - 8.kmac_test_vectors_sha3_224.27964045989066754543803650862129434572126339579673954929990421122569089160430
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:308172e1-46eb-40f3-a21e-f77680be3590
```
  - 19.kmac_test_vectors_sha3_224.67821477110304228515064099655614700299299685350163595194766767640583685793888
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/19.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:86512019-d0b1-4093-b262-6a6f595aa362
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.105061190992389573109372346142121493661733660796275985743866318759093841835156
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108304785 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108304785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.101834271879582179395177317723995601797594672754759789856647074791878027920763
    Line 379, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42701717163 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 42701717163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_entropy_refresh has 2 failures.

2.kmac_entropy_refresh.76120194534150273800427284552612202267528076152615454231511029585842753636413
Line 303, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3969963955 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (25 [0x19] vs 238 [0xee]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3969963955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_entropy_refresh.72982720753107330599117694962382170864430213872373751943842231763219297905594
Line 661, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 10076597447 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 39 [0x27]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10076597447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 1 failures.

3.kmac_app_with_partial_data.30913426457274171438006154784006576013534981511651213422168359294157815302219
Line 283, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 1333956748 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (19 [0x13] vs 45 [0x2d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1333956748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

23.kmac_app.88231875049184900506638105996811321990260117599120075288033300387013452831657
Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 3781002474 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (172 [0xac] vs 162 [0xa2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3781002474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

23.kmac_stress_all.49295204537489554611247130571014260359371107447122413870689726435885811088820
Line 331, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5381844474 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (217 [0xd9] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5381844474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.35991565369551705225013375897474479751067212633676752441905128439324557294311
    Line 1434, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50227759597 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 50227759597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 17.kmac_shadow_reg_errors_with_csr_rw.15197289208290439872127781972079045734471009449305906222949031532793651894418
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  21556107 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (236214484 [0xe1458d4] vs 0 [0x0]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
  UVM_INFO @  21556107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 28.kmac_key_error.92322288241664798588663909381093691855431821584567141880216554384223193568325
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 161232739 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 161232739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```