KMAC/UNMASKED Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.132m 11.113ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.090s 200.596us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.110s 29.468us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 19.780s 6.527ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 9.240s 538.173us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.520s 349.863us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.110s 29.468us 20 20 100.00
kmac_csr_aliasing 9.240s 538.173us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.710s 15.656us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.360s 39.841us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 59.521m 249.726ms 39 50 78.00
V2 burst_write kmac_burst_write 17.528m 54.481ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 59.256m 474.831ms 47 50 94.00
kmac_test_vectors_sha3_256 58.764m 576.870ms 50 50 100.00
kmac_test_vectors_sha3_384 42.246m 299.133ms 50 50 100.00
kmac_test_vectors_sha3_512 26.784m 204.148ms 50 50 100.00
kmac_test_vectors_shake_128 1.683h 181.373ms 26 50 52.00
kmac_test_vectors_shake_256 1.358h 182.116ms 18 50 36.00
kmac_test_vectors_kmac 5.960s 265.999us 50 50 100.00
kmac_test_vectors_kmac_xof 6.460s 2.495ms 50 50 100.00
V2 sideload kmac_sideload 8.206m 30.353ms 50 50 100.00
V2 app kmac_app 7.600m 80.387ms 49 50 98.00
V2 app_with_partial_data kmac_app_with_partial_data 5.877m 15.936ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 6.417m 27.886ms 50 50 100.00
V2 error kmac_error 8.583m 158.206ms 50 50 100.00
V2 key_error kmac_key_error 12.680s 19.678ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 45.830s 24.605ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 33.340s 542.238us 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.078m 26.835ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 32.400s 2.239ms 50 50 100.00
V2 stress_all kmac_stress_all 59.807m 962.726ms 50 50 100.00
V2 intr_test kmac_intr_test 0.850s 17.730us 50 50 100.00
V2 alert_test kmac_alert_test 0.890s 69.189us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.680s 120.322us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.680s 120.322us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.090s 200.596us 5 5 100.00
kmac_csr_rw 1.110s 29.468us 20 20 100.00
kmac_csr_aliasing 9.240s 538.173us 5 5 100.00
kmac_same_csr_outstanding 2.460s 221.327us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.090s 200.596us 5 5 100.00
kmac_csr_rw 1.110s 29.468us 20 20 100.00
kmac_csr_aliasing 9.240s 538.173us 5 5 100.00
kmac_same_csr_outstanding 2.460s 221.327us 20 20 100.00
V2 TOTAL 979 1050 93.24
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.640s 75.258us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.640s 75.258us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.640s 75.258us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.640s 75.258us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.150s 497.406us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.326m 6.515ms 5 5 100.00
kmac_tl_intg_err 5.130s 2.147ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.130s 2.147ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 32.400s 2.239ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.132m 11.113ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 8.206m 30.353ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.640s 75.258us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.326m 6.515ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.326m 6.515ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.326m 6.515ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.132m 11.113ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 32.400s 2.239ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.326m 6.515ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 6.174m 34.642ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.132m 11.113ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 25.324m 110.573ms 4 10 40.00
V3 TOTAL 4 10 40.00
TOTAL 1173 1250 93.84

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 20 80.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.21 95.89 92.30 100.00 67.77 94.11 98.84 96.58

Failure Buckets

Past Results