KMAC/UNMASKED Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.247m	45.821ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	115.822us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.160s	34.404us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.930s	4.021ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.100s	556.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.520s	103.204us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.160s	34.404us	20	20	100.00
		kmac_csr_aliasing	8.100s	556.169us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	21.563us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.530s	45.328us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.532m	26.542ms	41	50	82.00
V2	burst_write	kmac_burst_write	19.408m	200.309ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.794m	482.272ms	49	50	98.00
		kmac_test_vectors_sha3_256	56.904m	1.022s	50	50	100.00
		kmac_test_vectors_sha3_384	40.524m	292.593ms	50	50	100.00
		kmac_test_vectors_sha3_512	26.076m	100.855ms	50	50	100.00
		kmac_test_vectors_shake_128	1.707h	232.423ms	12	50	24.00
		kmac_test_vectors_shake_256	1.362h	181.040ms	19	50	38.00
		kmac_test_vectors_kmac	5.680s	247.055us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.260s	3.055ms	50	50	100.00
V2	sideload	kmac_sideload	8.393m	32.276ms	50	50	100.00
V2	app	kmac_app	5.618m	12.455ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.919m	40.695ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.696m	76.506ms	49	50	98.00
V2	error	kmac_error	8.093m	21.726ms	50	50	100.00
V2	key_error	kmac_key_error	17.850s	29.303ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.040s	4.749ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.570s	12.764ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	50.180s	5.482ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.020s	694.528us	50	50	100.00
V2	stress_all	kmac_stress_all	47.808m	223.001ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.830s	27.405us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	61.199us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.830s	329.947us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.830s	329.947us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	115.822us	5	5	100.00
		kmac_csr_rw	1.160s	34.404us	20	20	100.00
		kmac_csr_aliasing	8.100s	556.169us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	107.067us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	115.822us	5	5	100.00
		kmac_csr_rw	1.160s	34.404us	20	20	100.00
		kmac_csr_aliasing	8.100s	556.169us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	107.067us	20	20	100.00
V2		TOTAL			968	1050	92.19
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.450s	52.689us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.450s	52.689us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.450s	52.689us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.450s	52.689us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.970s	121.832us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.293m	25.646ms	5	5	100.00
		kmac_tl_intg_err	5.070s	290.599us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.070s	290.599us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.020s	694.528us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.247m	45.821ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.393m	32.276ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.450s	52.689us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.293m	25.646ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.293m	25.646ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.293m	25.646ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.247m	45.821ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.020s	694.528us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.293m	25.646ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.267m	58.777ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.247m	45.821ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	30.107m	51.553ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			1159	1250	92.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.01	95.89	92.30	100.00	66.94	94.11	98.84	96.01

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 79 failures:
- Test kmac_test_vectors_shake_256 has 31 failures.
  - 0.kmac_test_vectors_shake_256.107164028723104621411112929544572987394456761729343836172450841360898135448659
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:6e30f147-720f-4818-b338-1e27da05009c
```
  - 1.kmac_test_vectors_shake_256.83046138049946639372034773573164186759267572439890144659576409900381703001011
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:19c537f3-cae7-45a7-a8cf-b4d0464e4d45
```
  - ... and 29 more failures.
- Test kmac_long_msg_and_output has 9 failures.
  - 1.kmac_long_msg_and_output.104110445207497556571928655224714181751727955005189377827510025640709604776489
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:dd30b640-938e-4cbb-b02d-3be376eaa755
```
  - 5.kmac_long_msg_and_output.64499090529037888967602451033600010070769777938877126309295596058075736693486
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:a751a22c-3ca5-4397-b7b2-274516e22a65
```
  - ... and 7 more failures.
- Test kmac_test_vectors_shake_128 has 38 failures.
  - 1.kmac_test_vectors_shake_128.51330710353202849202630121768785491259743851961360885909452126826401138317883
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:7bc526c1-be7d-4495-9356-6da5b88ef735
```
  - 2.kmac_test_vectors_shake_128.22082379592003520826143746657398828778408350876173506392693936736265061934437
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:8351f60e-5243-477a-9529-43d745ea91c2
```
  - ... and 36 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 33.kmac_test_vectors_sha3_224.54708615996404575894710871144228315531697613216083521624311821222136470693481
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:d935b1dc-1b57-4f2a-99e0-1f7929fc36bd
```

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.59027456213490499633924727101984413044624752534374360078267389626171134784122
Line 345, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 20879928846 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (102 [0x66] vs 209 [0xd1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20879928846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

1.kmac_entropy_refresh.102690402855421520533683703942106942802530956961182686470450408103126763088398
Line 483, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4458523707 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (37 [0x25] vs 212 [0xd4]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4458523707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

1.kmac_mubi.4556536677657316353240145623510207561972316730403905592255610412681667049507
Line 657, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_mubi/latest/run.log

  UVM_FATAL @ 20850503762 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 128 [0x80]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 20850503762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

11.kmac_stress_all.56370212808391331743251465666341639432880920110220672409263929462449502109558
Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_FATAL @ 129902951955 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (124 [0x7c] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 129902951955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.21206037017958123984033871750339286924650334219098713632079043552726005894968
    Line 1673, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 185223464528 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 185223464528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.25520075471506386400236116022595651753515840079717611060852431254489938659307
    Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  66346940 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @  66346940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.11717362694297142734648653222203453105456314785382045859961167301501088659395
    Line 1033, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107840087972 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107840087972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.37734393064828933153193637725608105709908035336696164991685459697972501215551
    Line 2226, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51553322832 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51553322832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.