KMAC/UNMASKED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.147m	16.290ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.020s	26.738us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	102.975us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.520s	964.269us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.200s	2.063ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.510s	74.313us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	102.975us	20	20	100.00
		kmac_csr_aliasing	10.200s	2.063ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	17.592us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	43.841us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.146m	107.819ms	44	50	88.00
V2	burst_write	kmac_burst_write	18.411m	103.969ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.869m	97.400ms	49	50	98.00
		kmac_test_vectors_sha3_256	59.016m	1.290s	50	50	100.00
		kmac_test_vectors_sha3_384	39.353m	73.195ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.892m	51.455ms	50	50	100.00
		kmac_test_vectors_shake_128	1.578h	189.690ms	14	50	28.00
		kmac_test_vectors_shake_256	1.335h	228.710ms	22	50	44.00
		kmac_test_vectors_kmac	5.660s	502.638us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.030s	2.659ms	50	50	100.00
V2	sideload	kmac_sideload	8.682m	204.793ms	50	50	100.00
V2	app	kmac_app	6.223m	22.800ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.658m	32.976ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.650m	37.841ms	50	50	100.00
V2	error	kmac_error	8.190m	39.157ms	50	50	100.00
V2	key_error	kmac_key_error	12.720s	15.146ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.790s	1.559ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.710s	2.602ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.054m	34.915ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	31.210s	708.321us	50	50	100.00
V2	stress_all	kmac_stress_all	55.633m	382.888ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.930s	15.404us	50	50	100.00
V2	alert_test	kmac_alert_test	0.850s	102.188us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.840s	1.926ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.840s	1.926ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.020s	26.738us	5	5	100.00
		kmac_csr_rw	1.190s	102.975us	20	20	100.00
		kmac_csr_aliasing	10.200s	2.063ms	5	5	100.00
		kmac_same_csr_outstanding	2.570s	379.802us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.020s	26.738us	5	5	100.00
		kmac_csr_rw	1.190s	102.975us	20	20	100.00
		kmac_csr_aliasing	10.200s	2.063ms	5	5	100.00
		kmac_same_csr_outstanding	2.570s	379.802us	20	20	100.00
V2		TOTAL			973	1050	92.67
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.340s	86.294us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.340s	86.294us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.340s	86.294us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.340s	86.294us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.180s	160.493us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.029m	9.277ms	5	5	100.00
		kmac_tl_intg_err	5.200s	277.108us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.200s	277.108us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	31.210s	708.321us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.147m	16.290ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.682m	204.793ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.340s	86.294us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.029m	9.277ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.029m	9.277ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.029m	9.277ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.147m	16.290ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	31.210s	708.321us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.029m	9.277ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.099m	17.713ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.147m	16.290ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.756m	211.072ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1165	1250	93.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.28	95.89	92.27	100.00	68.60	94.11	98.84	96.29

Failure Buckets

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 71 failures:
- Test kmac_long_msg_and_output has 6 failures.
  - 0.kmac_long_msg_and_output.62717493988382557211114057824451148052353621997695519269203461013508818434318
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:3202ef68-f9eb-4690-b77c-bbc849d70039
```
  - 2.kmac_long_msg_and_output.108674605120265713392745858075345888401045261927364652966362962794026650295878
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:04284222-bc7f-4105-bd25-bf5b35f837df
```
  - ... and 4 more failures.
- Test kmac_test_vectors_shake_128 has 36 failures.
  - 1.kmac_test_vectors_shake_128.29546240902535308691877228269515476711118230798897684502365289143546425843017
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:eeb86e0d-7224-4352-aa88-57d0c104d513
```
  - 2.kmac_test_vectors_shake_128.25874324384542757686991415271267541643016730579049129957036129864620149899540
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:d4f4385a-61fa-4202-9d64-d0706e91181e
```
  - ... and 34 more failures.
- Test kmac_test_vectors_shake_256 has 28 failures.
  - 4.kmac_test_vectors_shake_256.62662935251469683026150743158926986755554796255627348491344785550197244998147
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:ce86417a-9b3b-4191-8486-6ec7e7335508
```
  - 5.kmac_test_vectors_shake_256.16363655022208499249122215566035012797434292442544653383894844485107544769236
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:a0d4cd0b-a676-40f8-a122-e1deaa1dea56
```
  - ... and 26 more failures.
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 34.kmac_test_vectors_sha3_224.109943240746085656282820375026375542849109566780446453628833078919972176764439
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:b575e239-b4bb-4fe6-ba61-d41794914eb9
```
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.27514786602632475393792446439800991034664709695683528344780290575223690425068
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1198511173 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1198511173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.56285771369164812664813227444668644587711686611226620059091086724467501997407
    Line 2880, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89578139878 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 89578139878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 6 failures:

Test kmac_stress_all has 2 failures.

1.kmac_stress_all.47360926849239144663858494946161512311136101290054409974689933921065387381664
Line 1297, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all/latest/run.log

  UVM_FATAL @ 143411517523 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (3 [0x3] vs 42 [0x2a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 143411517523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.kmac_stress_all.80548560229137248382464843158329405764726770179274721739168260894593744573455
Line 1841, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_stress_all/latest/run.log

  UVM_FATAL @ 95712112694 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (199 [0xc7] vs 176 [0xb0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 95712112694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_mubi has 1 failures.

3.kmac_mubi.63204700671549954269941567241893383055879551939273865258218222744515775256228
Line 321, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 1225416564 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (55 [0x37] vs 154 [0x9a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1225416564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 3 failures.

23.kmac_app.87452886378828573127661103027660993076541764558129293033054553912158350562371
Line 295, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 706496738 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (30 [0x1e] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 706496738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.kmac_app.14706934196042960420108919764458431428313928470612287149031021690580841055288
Line 761, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_app/latest/run.log

  UVM_FATAL @ 2921717798 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (62 [0x3e] vs 136 [0x88]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2921717798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 16.kmac_key_error.108089984315638821406117148362112753224858243343018242623708237361593537129529
    Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/16.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 601312566 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 601312566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```