KMAC/UNMASKED Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.187m	4.366ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	36.378us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	119.189us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.550s	5.775ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.190s	392.587us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	307.694us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	119.189us	20	20	100.00
		kmac_csr_aliasing	9.190s	392.587us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	19.990us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	163.927us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.424h	204.814ms	45	50	90.00
V2	burst_write	kmac_burst_write	20.473m	72.653ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	49.481m	354.558ms	5	5	100.00
		kmac_test_vectors_sha3_256	46.225m	328.996ms	5	5	100.00
		kmac_test_vectors_sha3_384	34.005m	60.300ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.188m	106.607ms	5	5	100.00
		kmac_test_vectors_shake_128	36.178m	20.119ms	5	5	100.00
		kmac_test_vectors_shake_256	46.492m	59.604ms	5	5	100.00
		kmac_test_vectors_kmac	2.910s	218.374us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.250s	121.644us	5	5	100.00
V2	sideload	kmac_sideload	8.678m	22.278ms	50	50	100.00
V2	app	kmac_app	6.339m	34.241ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.979m	57.266ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.580m	79.778ms	48	50	96.00
V2	error	kmac_error	7.954m	167.051ms	49	50	98.00
V2	key_error	kmac_key_error	9.080s	5.598ms	48	50	96.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.200s	6.364ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.580s	2.180ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.500s	22.557ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.660s	4.051ms	50	50	100.00
V2	stress_all	kmac_stress_all	48.825m	241.626ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.850s	18.192us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	17.488us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.780s	1.564ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.780s	1.564ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	36.378us	5	5	100.00
		kmac_csr_rw	1.190s	119.189us	20	20	100.00
		kmac_csr_aliasing	9.190s	392.587us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	481.566us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	36.378us	5	5	100.00
		kmac_csr_rw	1.190s	119.189us	20	20	100.00
		kmac_csr_aliasing	9.190s	392.587us	5	5	100.00
		kmac_same_csr_outstanding	2.790s	481.566us	20	20	100.00
V2		TOTAL			677	690	98.12
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	177.279us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	177.279us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	177.279us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	177.279us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.050s	125.218us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.339m	6.227ms	5	5	100.00
		kmac_tl_intg_err	5.170s	238.050us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.170s	238.050us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.660s	4.051ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.187m	4.366ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.678m	22.278ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	177.279us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.339m	6.227ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.339m	6.227ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.339m	6.227ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.187m	4.366ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.660s	4.051ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.339m	6.227ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.588m	37.084ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.187m	4.366ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.589m	2.522ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			868	890	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.21	95.89	92.27	100.00	67.77	94.11	98.84	96.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.27694106243967510575865882495476217656547492165001768497984893900870458174153
    Line 322, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2287522067 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2287522067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.39266856137815770460175733856491896588149441740878514787428452011670099872142
    Line 302, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2786967383 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2786967383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 1 failures.

1.kmac_app.70413310104532303898440583378532701812446296292185898164450778527233347439358
Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 384697071 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (71 [0x47] vs 129 [0x81]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 384697071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

2.kmac_stress_all.16220429014537140654984014459565906009823724167604476677911237686560094283721
Line 1579, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_FATAL @ 31680739554 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (173 [0xad] vs 253 [0xfd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31680739554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.kmac_stress_all.96045635792037300852722159497171755165521520048377697481415815108553163475500
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/36.kmac_stress_all/latest/run.log

  UVM_FATAL @ 8336326007 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (20 [0x14] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8336326007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 2 failures.

17.kmac_entropy_refresh.9233806558122871482849897608743010055716166916853470291634587866426008921853
Line 429, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 19621569467 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (56 [0x38] vs 87 [0x57]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 19621569467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_entropy_refresh.115166645380709456006042902402391692788989158510916213973623398671254561477800
Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/49.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 219351774 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (121 [0x79] vs 170 [0xaa]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 219351774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test kmac_long_msg_and_output has 5 failures.
  - 8.kmac_long_msg_and_output.97369879835038284113894152122972496395864168219666028865472090395930433754109
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:9615560f-cc82-417b-a8e8-1ffa0f4b8cbe
```
  - 13.kmac_long_msg_and_output.98280533721904489703882041049259352798417312806243531122593398700540023978160
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:4a0a5dfb-e59d-46fc-9029-4dbe9c621a68
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 0.kmac_stress_all_with_rand_reset.1138003625075123110419986648649375745101668253185333173355557090886839157942
    Line 427, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2848041979 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2848041979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.83688217973731495842165784986254720637795584713982012846136948243271483219154
    Line 276, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 151847455 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 151847455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 11.kmac_key_error.18618897076870537026985991472383418134183597380733653139808949886096000081401
    Line 267, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 759982233 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 759982233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 38.kmac_error.20889368433558207289471478100494922504107969574035906893476547498563885974570
    Line 897, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/38.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 41.kmac_key_error.8461455968895574785734629667501596044436109591602549908554397421344408511856
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 467776877 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @ 467776877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```