KMAC/UNMASKED Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.341m	38.505ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	52.158us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	489.596us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.480s	1.739ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.600s	550.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.530s	812.589us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	489.596us	20	20	100.00
		kmac_csr_aliasing	9.600s	550.157us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	14.710us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.430s	38.712us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.194h	83.758ms	46	50	92.00
V2	burst_write	kmac_burst_write	18.606m	66.724ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.948m	75.120ms	5	5	100.00
		kmac_test_vectors_sha3_256	50.619m	85.455ms	5	5	100.00
		kmac_test_vectors_sha3_384	41.597m	138.540ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.906m	32.843ms	5	5	100.00
		kmac_test_vectors_shake_128	1.002h	282.494ms	5	5	100.00
		kmac_test_vectors_shake_256	53.160m	89.760ms	5	5	100.00
		kmac_test_vectors_kmac	2.980s	226.393us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.570s	103.517us	5	5	100.00
V2	sideload	kmac_sideload	9.123m	85.671ms	50	50	100.00
V2	app	kmac_app	6.378m	17.947ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.518m	23.069ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.617m	79.848ms	48	50	96.00
V2	error	kmac_error	7.659m	18.562ms	50	50	100.00
V2	key_error	kmac_key_error	12.040s	13.536ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.230s	4.849ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	53.320s	3.538ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.081m	27.760ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.960s	3.232ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.127h	137.505ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.810s	14.790us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	33.815us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.020s	337.329us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.020s	337.329us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	52.158us	5	5	100.00
		kmac_csr_rw	1.250s	489.596us	20	20	100.00
		kmac_csr_aliasing	9.600s	550.157us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	194.759us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	52.158us	5	5	100.00
		kmac_csr_rw	1.250s	489.596us	20	20	100.00
		kmac_csr_aliasing	9.600s	550.157us	5	5	100.00
		kmac_same_csr_outstanding	2.570s	194.759us	20	20	100.00
V2		TOTAL			679	690	98.41
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.610s	87.444us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.610s	87.444us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.610s	87.444us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.610s	87.444us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.660s	2.600ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	51.290s	19.413ms	5	5	100.00
		kmac_tl_intg_err	5.040s	2.578ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.040s	2.578ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.960s	3.232ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.341m	38.505ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.123m	85.671ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.610s	87.444us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	51.290s	19.413ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	51.290s	19.413ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	51.290s	19.413ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.341m	38.505ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.960s	3.232ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	51.290s	19.413ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.495m	95.831ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.341m	38.505ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.109m	4.140ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			870	890	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.01	95.89	92.27	100.00	66.94	94.11	98.84	96.01

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_app has 4 failures.

7.kmac_app.4513082792194795874652594209218750362175257463415433872208509442428025258992
Line 495, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app/latest/run.log

  UVM_FATAL @ 4151020271 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (200 [0xc8] vs 237 [0xed]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4151020271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_app.19726287333356855717833943408358305247001920977873276444807639291470538073946
Line 409, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_app/latest/run.log

  UVM_FATAL @ 857409419 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 85 [0x55]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 857409419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_entropy_refresh has 2 failures.

30.kmac_entropy_refresh.7605738380225649227132972928464020436455168264516177263084553556964539524255
Line 337, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3753796960 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (49 [0x31] vs 92 [0x5c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3753796960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.kmac_entropy_refresh.44708980849079376480940900345251948205657000087367254504450534211920191641771
Line 835, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 112717617013 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (132 [0x84] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 112717617013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

34.kmac_stress_all.10642108176018142379262473011901823839945682744198211942766193086516463000700
Line 371, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_stress_all/latest/run.log

  UVM_FATAL @ 5286409781 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (153 [0x99] vs 27 [0x1b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5286409781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.2321046302749278079803038506792688179142466980414210395329696836927978476734
    Line 294, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2625712981 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2625712981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.68824066290507648559253556472882542934277767028877130062999233948586553331995
    Line 306, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3991108928 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3991108928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Job kmac_unmasked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test kmac_long_msg_and_output has 4 failures.
  - 6.kmac_long_msg_and_output.24696938054237971121765307169198680701020958363610811981660621440371793595504
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:d59eee96-b07d-4c27-a32a-9f02f5006d14
```
  - 21.kmac_long_msg_and_output.107967803161353372007518005446503703166538847038240081171267370733012290925921
    Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/21.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:e3cc5abf-3e3e-42ec-83a2-dea8172ffb37
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 5.kmac_stress_all_with_rand_reset.111866394977160553661580999520629127900390379485351454954694693839346463037701
    Line 378, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2468868631 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2468868631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.20433109906346238140554567517473396090016389242323515287251058780704976835403
    Line 471, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1750800385 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1750800385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.