KMAC/UNMASKED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.607m	4.076ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.610s	57.525us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.500s	34.445us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.430s	3.866ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	13.760s	563.666us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.460s	344.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.500s	34.445us	20	20	100.00
		kmac_csr_aliasing	13.760s	563.666us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.050s	14.782us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	37.943us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.341h	547.833ms	50	50	100.00
V2	burst_write	kmac_burst_write	18.005m	48.068ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.379m	307.474ms	5	5	100.00
		kmac_test_vectors_sha3_256	34.005m	57.842ms	5	5	100.00
		kmac_test_vectors_sha3_384	31.681m	319.299ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.016m	123.218ms	5	5	100.00
		kmac_test_vectors_shake_128	50.720m	1.188s	5	5	100.00
		kmac_test_vectors_shake_256	6.197m	40.669ms	5	5	100.00
		kmac_test_vectors_kmac	3.770s	150.204us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.870s	314.966us	5	5	100.00
V2	sideload	kmac_sideload	9.025m	60.759ms	50	50	100.00
V2	app	kmac_app	6.874m	24.146ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.126m	51.776ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	8.470m	44.941ms	49	50	98.00
V2	error	kmac_error	11.712m	191.601ms	49	50	98.00
V2	key_error	kmac_key_error	16.790s	1.627ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.070s	3.650ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.570s	1.567ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.532m	5.861ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.050s	911.231us	50	50	100.00
V2	stress_all	kmac_stress_all	35.172m	24.355ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.170s	23.728us	50	50	100.00
V2	alert_test	kmac_alert_test	1.310s	21.609us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.540s	185.334us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.540s	185.334us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.610s	57.525us	5	5	100.00
		kmac_csr_rw	1.500s	34.445us	20	20	100.00
		kmac_csr_aliasing	13.760s	563.666us	5	5	100.00
		kmac_same_csr_outstanding	3.190s	396.779us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.610s	57.525us	5	5	100.00
		kmac_csr_rw	1.500s	34.445us	20	20	100.00
		kmac_csr_aliasing	13.760s	563.666us	5	5	100.00
		kmac_same_csr_outstanding	3.190s	396.779us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.830s	49.101us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.830s	49.101us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.830s	49.101us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.830s	49.101us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.760s	478.830us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.413m	4.745ms	5	5	100.00
		kmac_tl_intg_err	7.090s	2.460ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.090s	2.460ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.050s	911.231us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.607m	4.076ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.025m	60.759ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.830s	49.101us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.413m	4.745ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.413m	4.745ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.413m	4.745ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.607m	4.076ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.050s	911.231us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.413m	4.745ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.003m	59.225ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.607m	4.076ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.860m	11.251ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			877	890	98.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.05	95.89	92.27	100.00	66.94	94.11	98.84	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test kmac_stress_all_with_rand_reset has 7 failures.

    • 0.kmac_stress_all_with_rand_reset.57436368161113805879835145809375628643843395591854042504473875939035344299962
      Line 97, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 307333907 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 307333907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.79108701648941275426975742847803313808648828125044951525705695993947752372920
      Line 73, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 762614762 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 762614762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_entropy_refresh has 1 failures.

    • 19.kmac_entropy_refresh.22582705670549767751067259307063268622499847237258491691504203364359064134389
      Line 370, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/19.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 9991575597 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (34 [0x22] vs 64 [0x40]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 9991575597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_app has 1 failures.

    • 22.kmac_app.41127809465474060207432523628946416851575351491296760211882014019924447880198
      Line 148, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/22.kmac_app/latest/run.log

        UVM_FATAL @ 5389526616 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (90 [0x5a] vs 126 [0x7e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 5389526616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.cfg_regwen has 1 failures:

  • Test kmac_app_with_partial_data has 1 failures.

    • 3.kmac_app_with_partial_data.41496487601696063982540950535621649689537943833640655695268469771608508046537
      Line 689, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/3.kmac_app_with_partial_data/latest/run.log

        UVM_ERROR @ 12252270169 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: kmac_reg_block.cfg_regwen
        UVM_INFO @ 12252270169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 6.kmac_stress_all_with_rand_reset.91208849580239155984703270588523221966743613556067064055929452466401886246663
      Line 442, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3384954069 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3384954069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 10.kmac_shadow_reg_errors_with_csr_rw.86060660949715895106432133027982668657032471121645842536569401482435559565017
      Line 77, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  14725689 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2484558248 [0x941759a8] vs 0 [0x0]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
        UVM_INFO @  14725689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 46.kmac_error.108230088435965564601416190996424400687379596300638824400322225310083103568089
      Line 1018, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/kmac_unmasked-sim-vcs/46.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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