KMAC/UNMASKED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.008m	4.167ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.070s	32.280us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.040s	405.911us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.880s	965.154us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.340s	1.009ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.430s	93.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.040s	405.911us	20	20	100.00
		kmac_csr_aliasing	8.340s	1.009ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.670s	11.598us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.330s	153.010us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.280h	1.031s	50	50	100.00
V2	burst_write	kmac_burst_write	14.758m	33.236ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.014m	121.278ms	5	5	100.00
		kmac_test_vectors_sha3_256	21.693m	17.003ms	5	5	100.00
		kmac_test_vectors_sha3_384	23.994m	246.087ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.854m	64.603ms	5	5	100.00
		kmac_test_vectors_shake_128	3.408m	19.335ms	5	5	100.00
		kmac_test_vectors_shake_256	33.243m	92.058ms	5	5	100.00
		kmac_test_vectors_kmac	2.370s	442.622us	5	5	100.00
		kmac_test_vectors_kmac_xof	2.140s	82.199us	5	5	100.00
V2	sideload	kmac_sideload	5.736m	199.607ms	50	50	100.00
V2	app	kmac_app	4.700m	70.449ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.226m	60.189ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.301m	108.084ms	50	50	100.00
V2	error	kmac_error	6.516m	46.839ms	50	50	100.00
V2	key_error	kmac_key_error	9.900s	6.870ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.560s	4.585ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	34.250s	2.264ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	51.570s	6.602ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	20.650s	5.037ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.007m	29.182ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.830s	26.132us	50	50	100.00
V2	alert_test	kmac_alert_test	0.790s	267.226us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.130s	616.982us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.130s	616.982us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.070s	32.280us	5	5	100.00
		kmac_csr_rw	1.040s	405.911us	20	20	100.00
		kmac_csr_aliasing	8.340s	1.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.410s	236.632us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.070s	32.280us	5	5	100.00
		kmac_csr_rw	1.040s	405.911us	20	20	100.00
		kmac_csr_aliasing	8.340s	1.009ms	5	5	100.00
		kmac_same_csr_outstanding	2.410s	236.632us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.200s	91.779us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.200s	91.779us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.200s	91.779us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.200s	91.779us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.610s	489.896us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.023m	5.189ms	5	5	100.00
		kmac_tl_intg_err	4.360s	398.907us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.360s	398.907us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	20.650s	5.037ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.008m	4.167ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.736m	199.607ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.200s	91.779us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.023m	5.189ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.023m	5.189ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.023m	5.189ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.008m	4.167ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	20.650s	5.037ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.023m	5.189ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.955m	9.717ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.008m	4.167ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.478m	9.549ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			878	890	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.88	95.80	90.59	100.00	67.77	93.74	99.00	96.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 0.kmac_stress_all_with_rand_reset.101534440636068609775910455760142562877756173130057758734140325782648326446885
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 896625248 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 896625248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.91620853726070386166979943303779976175635415864090898657942583350441292445237
    Line 71, in log /workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2605587810 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2605587810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_stress_all has 2 failures.

17.kmac_stress_all.88231845619259109747457020102723947324758064767080096042739395653726529024503
Line 888, in log /workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest/run.log

  UVM_FATAL @ 10389339077 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (113 [0x71] vs 243 [0xf3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10389339077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_stress_all.68720971837073388516303347597905330705871519253712951454034599833013225346756
Line 1020, in log /workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_FATAL @ 21707442204 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (122 [0x7a] vs 182 [0xb6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21707442204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.39877362112125411513188553315030538044975784189163292388088916479695549456110
    Line 119, in log /workspaces/repo/scratch/os_regression_2024_08_22/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2307569525 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2307569525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```