KMAC/UNMASKED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.684m	4.169ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.780s	29.411us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.810s	29.727us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	29.920s	1.499ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	14.900s	2.153ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.340s	78.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	29.727us	20	20	100.00
		kmac_csr_aliasing	14.900s	2.153ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.210s	18.214us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.530s	501.093us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.182h	369.526ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.842m	256.506ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	56.436m	334.354ms	5	5	100.00
		kmac_test_vectors_sha3_256	41.940m	93.545ms	5	5	100.00
		kmac_test_vectors_sha3_384	32.837m	223.988ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.769m	132.429ms	5	5	100.00
		kmac_test_vectors_shake_128	54.317m	388.509ms	5	5	100.00
		kmac_test_vectors_shake_256	38.774m	244.663ms	5	5	100.00
		kmac_test_vectors_kmac	3.900s	277.814us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.380s	225.034us	5	5	100.00
V2	sideload	kmac_sideload	9.053m	52.364ms	50	50	100.00
V2	app	kmac_app	8.751m	39.676ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.924m	33.175ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.637m	244.787ms	50	50	100.00
V2	error	kmac_error	8.795m	193.073ms	50	50	100.00
V2	key_error	kmac_key_error	20.480s	1.954ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.282m	24.580ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	56.530s	14.139ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.305m	7.381ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.010s	1.054ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.848m	213.258ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.340s	28.547us	50	50	100.00
V2	alert_test	kmac_alert_test	1.420s	20.426us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.760s	486.678us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.760s	486.678us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.780s	29.411us	5	5	100.00
		kmac_csr_rw	1.810s	29.727us	20	20	100.00
		kmac_csr_aliasing	14.900s	2.153ms	5	5	100.00
		kmac_same_csr_outstanding	4.100s	111.730us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.780s	29.411us	5	5	100.00
		kmac_csr_rw	1.810s	29.727us	20	20	100.00
		kmac_csr_aliasing	14.900s	2.153ms	5	5	100.00
		kmac_same_csr_outstanding	4.100s	111.730us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	98.442us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	98.442us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	98.442us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	98.442us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.660s	882.878us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.049m	20.136ms	5	5	100.00
		kmac_tl_intg_err	7.680s	285.854us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.680s	285.854us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.010s	1.054ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.684m	4.169ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.053m	52.364ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	98.442us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.049m	20.136ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.049m	20.136ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.049m	20.136ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.684m	4.169ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.010s	1.054ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.049m	20.136ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.641m	121.254ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.684m	4.169ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.745m	30.599ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			883	890	99.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.95	95.87	92.30	100.00	66.12	94.08	98.87	96.43

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.108000364022613277505303584129264922191743607584078198418746051538212390170525
    Line 283, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3836902252 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3836902252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.110150709106754847710180601581814902406689918293293853673423752394726278603358
    Line 421, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13504062414 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 13504062414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 13.kmac_key_error.79829716014186396328160796041640128679033942882347322676647924966412304558205
    Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1015319269 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1015319269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 13.kmac_shadow_reg_errors_with_csr_rw.45018664024768217700235173792428114662998309617983404578762644379354561270536
    Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_23/kmac_unmasked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  33219053 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2264004523 [0x86f1f7ab] vs 0 [0x0]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
  UVM_INFO @  33219053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `78ad89d1aa`