KMAC/UNMASKED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.285m	9.468ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	380.872us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.810s	321.252us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.160s	971.833us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	15.210s	3.796ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.630s	72.471us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	321.252us	20	20	100.00
		kmac_csr_aliasing	15.210s	3.796ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.140s	12.449us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.250s	62.737us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.546m	88.265ms	50	50	100.00
V2	burst_write	kmac_burst_write	17.900m	109.630ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.015m	241.756ms	5	5	100.00
		kmac_test_vectors_sha3_256	37.662m	237.383ms	5	5	100.00
		kmac_test_vectors_sha3_384	30.405m	233.810ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.651m	97.196ms	5	5	100.00
		kmac_test_vectors_shake_128	47.885m	246.569ms	5	5	100.00
		kmac_test_vectors_shake_256	46.596m	343.795ms	5	5	100.00
		kmac_test_vectors_kmac	3.610s	83.940us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.790s	261.861us	5	5	100.00
V2	sideload	kmac_sideload	10.128m	260.311ms	50	50	100.00
V2	app	kmac_app	7.118m	14.303ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.900m	177.723ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.697m	24.372ms	50	50	100.00
V2	error	kmac_error	7.023m	20.290ms	50	50	100.00
V2	key_error	kmac_key_error	22.670s	12.053ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.670s	1.871ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.069m	8.281ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.446m	6.356ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	41.170s	872.651us	50	50	100.00
V2	stress_all	kmac_stress_all	49.154m	969.552ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.260s	15.339us	50	50	100.00
V2	alert_test	kmac_alert_test	1.380s	47.568us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.480s	1.006ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.480s	1.006ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	380.872us	5	5	100.00
		kmac_csr_rw	1.810s	321.252us	20	20	100.00
		kmac_csr_aliasing	15.210s	3.796ms	5	5	100.00
		kmac_same_csr_outstanding	3.010s	39.530us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	380.872us	5	5	100.00
		kmac_csr_rw	1.810s	321.252us	20	20	100.00
		kmac_csr_aliasing	15.210s	3.796ms	5	5	100.00
		kmac_same_csr_outstanding	3.010s	39.530us	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.290s	61.239us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.290s	61.239us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.290s	61.239us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.290s	61.239us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.910s	604.446us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.895m	35.415ms	5	5	100.00
		kmac_tl_intg_err	6.690s	475.822us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.690s	475.822us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	41.170s	872.651us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.285m	9.468ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.128m	260.311ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.290s	61.239us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.895m	35.415ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.895m	35.415ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.895m	35.415ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.285m	9.468ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	41.170s	872.651us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.895m	35.415ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.161m	69.710ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.285m	9.468ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.764m	3.001ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			882	890	99.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.35	95.87	92.30	100.00	68.60	94.08	98.87	96.72

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 0.kmac_stress_all_with_rand_reset.98797106468230130103354437839992262397863822790002770472880116149440129919500
      Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1089616391 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1089616391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.kmac_stress_all_with_rand_reset.115638031743341780683100380441698368672999814409855398048097192042073405187197
      Line 220, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1114648028 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1114648028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.86081089380021925204122752736898213339740507723238113124817835479445208204627
      Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @   3982235 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (316 [0x13c] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period reset value: 0x0
        UVM_INFO @   3982235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 1.kmac_stress_all_with_rand_reset.62245984328141042259468356775657128906753080020518476927979330643090451474120
      Line 386, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24817002820 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24817002820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 17.kmac_key_error.40244011065303045376304877156119267872113160120871899077541048594314721079303
      Line 90, in log /workspaces/repo/scratch/os_regression_2024_09_17/kmac_unmasked-sim-vcs/17.kmac_key_error/latest/run.log

        UVM_ERROR @ 1269134473 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
        UVM_INFO @ 1269134473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.12_10.16.22
• 2024.09.10_08.11.14
• 2024.09.05_04.20.46
• 2024.09.02_11.30.33
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• 2024.08.26_02.17.22