KMAC/UNMASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.451m	4.222ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.670s	18.826us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.730s	99.999us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	33.150s	5.328ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.240s	210.676us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.950s	265.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.730s	99.999us	20	20	100.00
		kmac_csr_aliasing	11.240s	210.676us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.130s	36.825us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.200s	19.857us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.206h	486.229ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.018m	201.074ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.613m	364.925ms	5	5	100.00
		kmac_test_vectors_sha3_256	28.467m	17.265ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.357m	187.543ms	5	5	100.00
		kmac_test_vectors_sha3_512	23.935m	267.680ms	5	5	100.00
		kmac_test_vectors_shake_128	45.162m	140.378ms	5	5	100.00
		kmac_test_vectors_shake_256	46.661m	362.902ms	5	5	100.00
		kmac_test_vectors_kmac	3.830s	86.537us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.430s	121.144us	5	5	100.00
V2	sideload	kmac_sideload	8.358m	137.399ms	50	50	100.00
V2	app	kmac_app	6.913m	14.461ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.184m	27.647ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.033m	63.954ms	50	50	100.00
V2	error	kmac_error	8.208m	160.680ms	50	50	100.00
V2	key_error	kmac_key_error	20.000s	10.047ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.760s	1.836ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	59.330s	31.869ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	2.034m	31.875ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	32.150s	2.884ms	50	50	100.00
V2	stress_all	kmac_stress_all	53.947m	108.302ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.270s	52.131us	50	50	100.00
V2	alert_test	kmac_alert_test	1.350s	112.753us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	7.310s	165.497us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	7.310s	165.497us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.670s	18.826us	5	5	100.00
		kmac_csr_rw	1.730s	99.999us	20	20	100.00
		kmac_csr_aliasing	11.240s	210.676us	5	5	100.00
		kmac_same_csr_outstanding	4.830s	1.791ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.670s	18.826us	5	5	100.00
		kmac_csr_rw	1.730s	99.999us	20	20	100.00
		kmac_csr_aliasing	11.240s	210.676us	5	5	100.00
		kmac_same_csr_outstanding	4.830s	1.791ms	20	20	100.00
V2		TOTAL			689	690	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.360s	67.176us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.360s	67.176us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.360s	67.176us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.360s	67.176us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.470s	547.428us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.487m	5.229ms	5	5	100.00
		kmac_tl_intg_err	7.230s	233.455us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.230s	233.455us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	32.150s	2.884ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.451m	4.222ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.358m	137.399ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.360s	67.176us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.487m	5.229ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.487m	5.229ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.487m	5.229ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.451m	4.222ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	32.150s	2.884ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.487m	5.229ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.920m	72.348ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.451m	4.222ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	7.184m	21.011ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			882	890	99.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.27	95.89	92.30	100.00	68.60	94.11	98.84	96.15

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.75976586405893064750938983012861621971474063983721271951567292255971797554621
    Line 229, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5658014331 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5658014331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.46410557098010779757081750171902074724748568934465540964631766838373621743512
    Line 259, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1695782215 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1695782215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.96471822973040102761571019105754883677368645853683601361920273847245037049292
    Line 377, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3266698186 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3266698186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 19.kmac_key_error.8391914203111940118709706989418201488060758697037557659802868288737133576377
    Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_10/kmac_unmasked-sim-vcs/19.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 368182132 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 368182132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KMAC/UNMASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25b1acbf68`