KMAC/UNMASKED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.468m	10.552ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.350s	46.377us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.430s	127.602us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.580s	9.058ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.600s	1.063ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.840s	159.161us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.430s	127.602us	20	20	100.00
		kmac_csr_aliasing	9.600s	1.063ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.970s	31.772us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.760s	133.089us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.612h	1.287s	50	50	100.00
V2	burst_write	kmac_burst_write	17.739m	56.216ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.998m	89.968ms	5	5	100.00
		kmac_test_vectors_sha3_256	39.078m	113.506ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.236m	48.815ms	5	5	100.00
		kmac_test_vectors_sha3_512	20.820m	160.831ms	5	5	100.00
		kmac_test_vectors_shake_128	52.101m	157.477ms	5	5	100.00
		kmac_test_vectors_shake_256	27.205m	17.400ms	5	5	100.00
		kmac_test_vectors_kmac	3.390s	303.518us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.660s	36.879us	5	5	100.00
V2	sideload	kmac_sideload	8.198m	97.552ms	50	50	100.00
V2	app	kmac_app	6.657m	64.928ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.613m	32.957ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.514m	77.946ms	50	50	100.00
V2	error	kmac_error	10.096m	21.667ms	48	50	96.00
V2	key_error	kmac_key_error	31.986s		49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	55.010s	5.347ms	19	20	95.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.013m	3.657ms	19	20	95.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.142m	4.144ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	27.560s	856.399us	50	50	100.00
V2	stress_all	kmac_stress_all	47.787m	143.696ms	50	50	100.00
V2	intr_test	kmac_intr_test	38.922s		40	50	80.00
V2	alert_test	kmac_alert_test	1.350s	93.438us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.040s	190.917us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.040s	190.917us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.350s	46.377us	5	5	100.00
		kmac_csr_rw	1.430s	127.602us	20	20	100.00
		kmac_csr_aliasing	9.600s	1.063ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	101.558us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.350s	46.377us	5	5	100.00
		kmac_csr_rw	1.430s	127.602us	20	20	100.00
		kmac_csr_aliasing	9.600s	1.063ms	5	5	100.00
		kmac_same_csr_outstanding	2.600s	101.558us	20	20	100.00
V2		TOTAL			675	690	97.83
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.670s	123.433us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.670s	123.433us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.670s	123.433us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.670s	123.433us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.330s	402.456us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.414m	10.436ms	5	5	100.00
		kmac_tl_intg_err	5.630s	395.336us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.630s	395.336us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	27.560s	856.399us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.468m	10.552ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.198m	97.552ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.670s	123.433us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.414m	10.436ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.414m	10.436ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.414m	10.436ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.468m	10.552ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	27.560s	856.399us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.414m	10.436ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.554m	33.133ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.468m	10.552ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.250m	3.332ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			869	890	97.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.25	95.87	92.34	100.00	68.60	94.08	98.87	96.01

Failure Buckets

Job returned non-zero exit code has 14 failures:

Test kmac_error has 1 failures.

0.kmac_error.18662488271026497700942938019336743890135356134008688734299197289508839988318
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_error/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_key_error has 1 failures.

0.kmac_key_error.109769249345711953949908611820645131582737301172415820931099878866472758192000
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_key_error/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_edn_timeout_error has 1 failures.

0.kmac_edn_timeout_error.79725923536163908015072858020336881846689829579707296389289837330822221052999
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_entropy_mode_error has 1 failures.

0.kmac_entropy_mode_error.23285164761365787101472679291481151839040338713571859488694110619954009468395
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test kmac_intr_test has 10 failures.

39.kmac_intr_test.23954749709920323810482613717271066352802245748409681750937337288715244595099
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/39.kmac_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

40.kmac_intr_test.56102993195028228125226888278528137504817276981858947315397737251523035021575
Log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/40.kmac_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  3 10:29 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 8 more failures.

UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 1.kmac_stress_all_with_rand_reset.107037521840749538248003323060575584471124705643913817033842925621848397348236
    Line 436, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14887043006 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14887043006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.6411335899074065828754785872966868581804429316082298117789677756117472731283
    Line 170, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2899746517 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2899746517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 4.kmac_stress_all_with_rand_reset.35641370541314164363290109893422070976368971144101690389483331432749328738287
    Line 104, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 547910515 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 547910515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.35751783045168141432259181359294794077207945111458750747008500575218966375470
    Line 86, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 129259202 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 129259202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.kmac_shadow_reg_errors_with_csr_rw.114130059510924074174767111617781665528594422917050044643693837343336043384514
    Line 77, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  40271860 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (462216925 [0x1b8cdedd] vs 1203322616 [0x47b93ef8]) Regname: kmac_reg_block.prefix_1 reset value: 0x0
  UVM_INFO @  40271860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 44.kmac_error.49987635965074263782621989010984014408767332120494889897849526431330501362792
    Line 680, in log /workspaces/repo/scratch/os_regression_2024_10_02/kmac_unmasked-sim-vcs/44.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```