KMAC/UNMASKED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.563m	8.253ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.810s	118.706us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.820s	33.935us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	25.130s	7.307ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.940s	144.390us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.020s	331.759us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	33.935us	20	20	100.00
		kmac_csr_aliasing	10.940s	144.390us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.160s	14.687us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.320s	148.089us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.340h	2.165s	50	50	100.00
V2	burst_write	kmac_burst_write	20.221m	34.639ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.118m	81.740ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.799m	58.910ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.332m	55.233ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.964m	94.331ms	5	5	100.00
		kmac_test_vectors_shake_128	34.410m	21.677ms	5	5	100.00
		kmac_test_vectors_shake_256	27.915m	67.461ms	5	5	100.00
		kmac_test_vectors_kmac	3.370s	76.347us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.390s	73.781us	5	5	100.00
V2	sideload	kmac_sideload	9.930m	114.693ms	50	50	100.00
V2	app	kmac_app	7.212m	16.186ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.350m	73.112ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.212m	15.402ms	50	50	100.00
V2	error	kmac_error	9.167m	18.782ms	50	50	100.00
V2	key_error	kmac_key_error	21.370s	7.481ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	50.900s	2.969ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.360s	7.280ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.478m	12.502ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	58.680s	8.525ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.167m	380.092ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.320s	232.619us	50	50	100.00
V2	alert_test	kmac_alert_test	1.440s	39.748us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.890s	606.920us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.890s	606.920us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.810s	118.706us	5	5	100.00
		kmac_csr_rw	1.820s	33.935us	20	20	100.00
		kmac_csr_aliasing	10.940s	144.390us	5	5	100.00
		kmac_same_csr_outstanding	4.230s	1.320ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.810s	118.706us	5	5	100.00
		kmac_csr_rw	1.820s	33.935us	20	20	100.00
		kmac_csr_aliasing	10.940s	144.390us	5	5	100.00
		kmac_same_csr_outstanding	4.230s	1.320ms	20	20	100.00
V2		TOTAL			690	690	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.290s	276.652us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.290s	276.652us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.290s	276.652us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.290s	276.652us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.030s	420.045us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.512m	11.710ms	5	5	100.00
		kmac_tl_intg_err	7.080s	237.101us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.080s	237.101us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	58.680s	8.525ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.563m	8.253ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.930m	114.693ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.290s	276.652us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.512m	11.710ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.512m	11.710ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.512m	11.710ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.563m	8.253ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	58.680s	8.525ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.512m	11.710ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.171m	54.111ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.563m	8.253ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.557m	2.047ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			884	890	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	25	100.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.23	95.87	92.30	100.00	68.60	94.08	98.87	95.86

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1196) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 0.kmac_stress_all_with_rand_reset.33410417130797956421135464261008953140987972178366370314793970409647170238499
      Line 282, in log /workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1956940351 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1956940351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.86132425216161526393632228052101137388486018832321300935339411458385943106889
      Line 85, in log /workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 164251738 ps: (kmac_scoreboard.sv:1196) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 164251738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 6.kmac_stress_all_with_rand_reset.96265572500338944784752454693638038991500007640894886585863644828915440460497
      Line 153, in log /workspaces/repo/scratch/os_regression_2024_10_08/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19079903344 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19079903344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.04_00.41.58
• 2024.09.25_11.00.59
• 2024.09.19_09.04.44
• 2024.09.12_10.16.22
• 2024.09.10_08.11.14
• 2024.09.05_04.20.46
• 2024.09.02_11.30.33