8a1401d614| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.615m | 4.114ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.550s | 19.127us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.640s | 184.071us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 13.370s | 293.989us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 11.980s | 2.549ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.480s | 294.061us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.640s | 184.071us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 11.980s | 2.549ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.090s | 31.813us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.770s | 25.592us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.392h | 264.936ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 22.993m | 282.392ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 34.959m | 61.103ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 39.312m | 142.163ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 27.823m | 124.800ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 22.221m | 62.165ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 33.181m | 21.193ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 40.569m | 121.217ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 4.280s | 413.114us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 4.390s | 110.399us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.187m | 138.668ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 5.694m | 32.480ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 5.875m | 28.115ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.915m | 23.675ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.251m | 16.083ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 17.760s | 7.400ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.950m | 10.063ms | 36 | 50 | 72.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 56.500s | 1.975ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 54.560s | 8.486ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.349m | 11.131ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 1.284m | 8.676ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 46.155m | 856.374ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.250s | 16.672us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.350s | 59.212us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 5.320s | 159.720us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 5.320s | 159.720us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.550s | 19.127us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.640s | 184.071us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.980s | 2.549ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.960s | 798.501us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.550s | 19.127us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.640s | 184.071us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 11.980s | 2.549ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.960s | 798.501us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 726 | 740 | 98.11 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.010s | 35.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.010s | 35.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.010s | 35.130us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.010s | 35.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 4.590s | 2.664ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.341m | 24.080ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.950s | 369.484us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.950s | 369.484us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 1.284m | 8.676ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.615m | 4.114ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.187m | 138.668ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.010s | 35.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.341m | 24.080ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.341m | 24.080ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.341m | 24.080ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.615m | 4.114ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 1.284m | 8.676ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.341m | 24.080ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.532m | 13.544ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.615m | 4.114ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 4.814m | 4.102ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 921 | 940 | 97.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 26 | 26 | 25 | 96.15 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.05 | 96.19 | 92.52 | 100.00 | 72.73 | 94.61 | 99.03 | 96.29 |
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
6.kmac_sideload_invalid.4403423599356574848605075715527188054976271045123779745518828058816360567267
Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10015426001 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe1a29000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10015426001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.kmac_sideload_invalid.20876178147852207959170804954316030173378865857908107525777375851578243189262
Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10264027963 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6a636000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10264027963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
4.kmac_stress_all_with_rand_reset.79351898491108758266137829382118069689135085680798924715509085986106850156460
Line 204, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14272354778 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14272354778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.28350837405306506389512028154228116105348130126700928597522827184914804712143
Line 182, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5382056767 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5382056767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
16.kmac_sideload_invalid.72375831617254680778947500931404791668277071244198194895364582206518593900665
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10075225190 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb2d5d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10075225190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_sideload_invalid.29521014628394463974857999383616779145200858887813822424263896272369981065553
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10011321480 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8814000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10011321480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
3.kmac_stress_all_with_rand_reset.33297125467638648099790728858530929303055499463204091542363392917141377006406
Line 75, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39984448 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
UVM_INFO @ 39984448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.kmac_stress_all_with_rand_reset.32127552552443343424102549516583157635199109158786088850976671570301001357718
Line 239, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11540350710 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
UVM_INFO @ 11540350710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
24.kmac_sideload_invalid.10588217519743084504466851001316491420934849988955674608280128050962620241793
Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10319703171 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf444c000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10319703171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.kmac_sideload_invalid.77759446831418358349860575102261246579885681220834164710176212346899938886305
Line 78, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10304026555 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x95578000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10304026555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
28.kmac_sideload_invalid.72879884140400075985282202281080503020497820890423446104572373946813734478643
Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10093344841 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x18055000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10093344841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.kmac_sideload_invalid.4741721826594439726205391468896478858670614135117043883793729928412425337054
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10050684358 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x231bf000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10050684358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
9.kmac_sideload_invalid.88644412116185588950599667866737294202184709238296378620865943311741380642751
Line 88, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10125565074 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd24db000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10125565074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
32.kmac_sideload_invalid.4086094519383556153198156233012828829206349674469670701438693631297756090541
Line 78, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10062665643 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xed62c000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10062665643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
48.kmac_sideload_invalid.89630507048000479931484602912095568093667493429955058414569160846519163031152
Line 92, in log /workspaces/repo/scratch/os_regression_2024_10_11/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10259897775 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2eab8000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10259897775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---