LC_CTRL Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	15.120s	276.779us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.220s	21.621us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	17.171us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.550s	65.176us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.270s	22.016us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.900s	43.702us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	17.171us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	22.016us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	16.750s	95.198us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.250s	734.619us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	12.954us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.790s	231.790us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	26.120s	963.108us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_prog_failure	4.790s	231.790us	50	50	100.00
		lc_ctrl_errors	26.120s	963.108us	50	50	100.00
		lc_ctrl_security_escalation	16.720s	427.840us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.816m	5.012ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.770s	1.195ms	20	20	100.00
		lc_ctrl_jtag_errors	1.995m	4.685ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.790s	913.607us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.440s	1.145ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	26.770s	1.195ms	20	20	100.00
		lc_ctrl_jtag_errors	1.995m	4.685ms	20	20	100.00
		lc_ctrl_jtag_access	22.300s	999.883us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	31.450s	6.747ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.210s	275.240us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.650s	189.185us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	51.400s	2.677ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.260s	1.395ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.030s	143.744us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.940s	134.154us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.980s	116.856us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.130s	3.155ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.210s	17.675us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.883m	27.069ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	29.582us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.250s	568.612us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.250s	568.612us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.220s	21.621us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	17.171us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	22.016us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	43.403us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.220s	21.621us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	17.171us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	22.016us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.860s	43.403us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.720s	193.814us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.720s	193.814us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.250s	734.619us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.069m	428.686us	50	50	100.00
		lc_ctrl_sec_cm	1.194m	1.998ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.720s	427.840us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	16.750s	95.198us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.440s	1.145ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	27.120s	693.501us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	27.120s	693.501us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.800s	639.328us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.320s	624.573us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.320s	624.573us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	16.822m	100.233ms	4	50	8.00
V3		TOTAL			4	50	8.00
		TOTAL			984	1030	95.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	97.18	95.43	91.98	100.00	95.88	98.48	95.18

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 30 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.1943058957
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0768acb2-cedc-41df-8ac2-e3b5af372e54
```
  - 1.lc_ctrl_stress_all_with_rand_reset.2857046781
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:18f511bb-bcbb-470d-bcb4-ae9bc15faa2d
```
  - ... and 28 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 8 failures.
  - 6.lc_ctrl_stress_all_with_rand_reset.2517832665
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fe3f0dc6-42c9-4997-98a5-8535ae41d7f9
```
  - 9.lc_ctrl_stress_all_with_rand_reset.2496927079
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:507da68f-c844-4d6c-a935-580182ceff17
```
  - ... and 6 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 5 failures:

Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

19.lc_ctrl_stress_all_with_rand_reset.1960397365
Line 14216, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16379127749 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x9cbb1c00
  UVM_INFO @ 16379127749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.lc_ctrl_stress_all_with_rand_reset.2552570429
Line 10403, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 13715307184 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x50164800
  UVM_INFO @ 13715307184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (lc_ctrl_scoreboard.sv:234) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

8.lc_ctrl_stress_all_with_rand_reset.1743071597
Line 7835, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7250370750 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked5
  UVM_INFO @ 7250370750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.lc_ctrl_stress_all_with_rand_reset.3349296392
Line 6432, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13700966928 ps: (lc_ctrl_scoreboard.sv:234) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 97, LC_St DecLcStTestUnlocked4
  UVM_INFO @ 13700966928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.transition_token_* reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.lc_ctrl_stress_all_with_rand_reset.4068044693
    Line 10617, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10989569064 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 787335593 [0x2eedc9a9]) Regname: lc_ctrl_reg_block.transition_token_2 reset value: 0x0
  UVM_INFO @ 10989569064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```